COMPUTER ARCHITECTURE (PoCA)

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COMPUTER ARCHITECTURE (PoCA) EKT303/4 PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Staffs Fazrul Faiz Zakaria Rafikha Aliana A.Raof Phaklen Ehkan ffaiz@unimap.edu.my Rafikha Aliana A.Raof rafikha@unimap.edu.my Phaklen Ehkan phaklen@unimap.edu.my Mohammad Nazri Md. Noor nazri@unimap.edu.my

Textbook

------- refer teaching plan-------- Contents (lecture) Chap. 1: Introduction to Comp. Architecture Chap. 2: Foundation to Comp. Architecture Chap. 3: Design Methodology Chap. 4: Central Processing Unit (CPU) Basics Chap. 5: Processor Internals Chap. 6: Enhancing CPU Performance Chap. 7: CPU Externals Chap. 8: Practical Embedded CPUs Chap. 9: Evolution of Computer Architecture ------- refer teaching plan--------

Laboratory VHDL as hardware programming Altera Quartus II as a development platform Altera DE FPGA board

Optimised Netlist (Gate level) VHDL – Design Flow VHDL entry compilation Netlist (Gate level) optimization synthesis Optimised Netlist (Gate level) simulation Place & route Physical device simulation

Code Structure – Fundamental VHDL units Library declaration Basic VHDL Code Entity Architecture

Example VHDL code for FA unit library ieee; use ieee.std_logic_1164.all; entity full_adder is port (a,b,cin : in bit; s, cout : out bit; end full_adder; architecture dataflow of full_adder is begin s <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END dataflow; circuit

Contact Hours Lecture: Laboratory: Wednesday: 08-10 (CompE), 10-12 (CommE), 13-15 (CompNetE) Thursday: 08-09 (CompE), 09-10 (CommE), 10-11 (CompNetE) Laboratory: Tuesday: 08-10 (CompE), 12-14 (CommE), 16-18 (CompNetE)

Test, Quiz & Assignment = 30% Lab. Component = 20% Final Exam = 50% Assessment Test, Quiz & Assignment = 30% Lab. Component = 20% Final Exam = 50%

End of Intro..