Binary or Gray How is better?

Modular/Scalable Gray counter Implementation of modular/Scalable Gray counter. Reason : The Myth is gray consumes lesser power than binary counter, since the next state transition differs only one bit from present state. Since if we were to compare the binary counter (including binary-to-Gray converter) with the Gray code counter, there are several things which need to be answered, How many logic gates are required for each implementation? How many levels of logic gates are there in the two feedback paths? What's the (relative) maximum frequency of each type of counter? What's the (relative) switching activity, noise, and power consumption of each type of counter? [Clive “Max” Maxfield is president of Maxfield High-Tech Consulting and editor of the EE Times Programmable Logic Designline]

Fundamentally the reason is correct until the things are software based. But when we freeze design on hardware the previous questions are unanswerable w.r.t Area, power, delay. If not then the paper “Some Issues in Gray Code Addressing” Incremented and then B2G Binary Incremented G2B Incremented and then B2G

Conversion system Again, if we think regarding Computation complexity, it concerns the efficiency of an algorithm. Big-0 notation: The computation time of an algorithm depends on the size of the input as well as on the type of processor, programming language, compiler and even personal coding style. Since, It is difficult to determine the exact time needed to complete execution of an algorithm. The order is defined as follows. Given two functions, f(n) and g(n), we say that f(n) is O(g(n)).

Scaling of some commonly used Big-0 functions REALIZATION OF VHDL OPERATORS : Logical operators can be mapped directly to logic gates, and their synthesis is straightforward. The and, nand, or, and nor operators have similar area and delay characteristics. The xor and xnor operators are slightly more involved and their implementation requires more silicon area and experiences a larger propagation delay.

Circuit area and delay of some commonly used VHDL operators Reference : PONG P. CHU, RTL HARDWARE DESIGN USING VHDL Coding for Efficiency, Portability, and Scalability

XOR activities Activity as a function of topology Transition probability of XOR gate with basic gates

Gray counter Next state Function table of a 4-bit Gray code incrementer Next state Although the VHDL code is simple, it is not scalable because the needed revision is on the order of 0(2n). Unfortunately, there is no easy algorithm to derive the next Gray code word directly.