Xilinx Spartan-6 FPGA Board Setup Jeremy Sandoval University of Washington

Table of Contents Hardware Overview: Xilinx Spartan-6 FPGA Relation to ATLAS IBL ROD Software Overview: Xilinx ISE Design Suite VHDL Programming Next Steps

Hardware Overview: Spartan-6 FPGA Field Programmable Gate Array The Spartan-6 family is built on a 45-nanometer [nm], 9-metal layer, dual-oxide process technology. The Spartan-6 was marketed in 2009 as a low-cost solution for automotive, wireless communications, flat-panel display and video surveillance applications Updated FPGA technology for ATLAS IBL ROD, Previous Read Out Driver utilized Spartan-2 FPGA Source: http://www.robotshop.com/content/images/digilent-atlys-spartan-6-fpga-development-kit-large.jpg

ATLAS Insertable B-Layer New pixel detector layer to be installed this year (2013) Will be integrated into the general pixel readout software framework ROD (Read Out Driver) Card will interface with 32 FE-I4 ASICs at a rate of 160 Mbit/s ROD card proposes two XILINX Spartan6 programmable devices and one Virtex5 with Power PC capabilities. Commercial devices allow for reuse of most of the VHDL code that was designed to implement the firmware on the current ROD card for the ATLAS pixel and SCT experiments Source (for both pictures): ATLAS IBL: Integration of new HW/SW readout features for the additional layer of Pixel Detector (PDF Flyer)

Xilinx ISE Software The Xilinx ISE (Integrated Software Environment) Design Suite is used for synthesis and analysis of HDL (Hardware Description Language) designs. Allows developer to: synthesize their design perform timing analysis examine RTL diagrams simulate a design’s reaction to different stimuli configure the target device with the programmer Learning how to use Xilinx ISE 14.4 Xilinx ISE 14.4 Screen Shot Source: forums.xilinx.com  

VHDL Very High-speed Integrated Circuit Hardware Description Language Xilinix provides training exercises and tutorials for beginner VHDL programmers who have experience coding in Verilog Completed two 1 hour training sessions: “Basic HDL Coding Techniques” “Virtex 6 and Spartan 6 HDL Coding Techniques” “FPGA Prototyping by VHDL Examples”, by Pong P. Chu Example Adder VHDL Code Source: http://en.wikipedia.org/wiki/File:Vhdl_signed_adder.png

Next Steps Continuing Xilinx VHDL tutorials and exercises Learn how to read/write/access registers on the Spartan-6 FPGA Continue becoming familiar with the Off Detector Read Out Architecture (described in IBLROD IEEE paper)