TORCH electronics 10 June 2010 Johan Fopma, University of Oxford LHCB-RICH-Upgrade TORCH electronics 10 June 2010 Johan Fopma, University of Oxford

A Time Of Flight detector using RICH technology. Design by Roger Forty Possible replacement for RICH 1 • Tracks emit Cherenkov photons in the quartz block. • Key point: determine wavelength, correct for chromatic dispersion. • Measure ToF of track from PV to quartz block. • ... combining measurements from many photons.

1cm-thick quartz plate at z=12m

Fitting in the front-end

THE FRONT END

128

Initial numbers 19 bits /hit. 80 bits / 25 ns slot / datalink 38 hits per 25 ns slot if we ignore the tail 38 hits X 19 bits = 722 bits / 25 ns slot We therefore need 722 / 80 = 9 datalinks/ MCP PMT to deal with this.

Updated Hit rate for an event (April 2010, Matthew Charles) LUMI 2 min bias 99% of distribution has ≤ 28 hits LUMI 20 min bias 99% of distribution has ≤ 71 hits

Time distribution of hits •We want overall time resolution of 20-30 ps from MCP-PMT. •We will for sure need to sample full 25ns range per BX. If we use 9-bit time index: • sample window = 25ns / 512 = 49 ps • contribution to resolution = window / √12 = 14 ps If we use 10-bit time index: • sample window = 25ns / 1024 = 24 ps • contribution to resolution = window / √12 = 7 ps

Hit Rate •The sustained rate for min-bias. • 7.7×106 hits per PMT per second for lumi2 • 7.5×107 hits per PMT per second for lumi20 • Assuming 20 bits per hit (10 for channel, 10 for time), we get per PMT a sustained rate of 0.15 Gb/s for lumi2, 1.5 Gb/s for lumi20.

Front End Readout test System 10, June 2010

Making a test board Choose a more pedestrian MCP-PMT 8 X 8: XP85012, 25 micron pore size Rise time 0.6 ns Pulse width 1.8 ns Add NINO chips and HPTDC Doing tests in the lab with dark box; later beam tests

A complete readout system

Board Diagram MCP connection, NINO x2, HPTDCx2 in very high resolution mode, Medium size Spartan3A/ Small Spartan-6, Optional RAM, Separate JTAGs for HPTDC through FPGA, 40Mhz external clock from motherboard via clock buffer, Xilinx configuration flash (not needed for Spartan 3AN

Main Components for Front End Readout Board Spartan 3AN XCS400AN, £21 360k block RAM, 311 user I/O (150 needed), Non-volatile configuration. Future choice: Spartan6 XC6XLS25T, Multi-Gigabit transceiver, 930k block RAM. Gigabit Ethernet Transceiver, £5~20 National Semiconductor DP83865/ Marvell ME88, Broadcom BCM5461 Reference design available from Xilinx evaluation boards, Connectors Samtec connector for MCP, £3GBP, Lemo 2pin socket £25, LVDS Clock Buffer, £10 SN65LVDS104D, PCB 160mmx 85mm, 8 layers £1000 for 10 boards Parts cost ~ £200 per boards exclude NINO and HPTDC.

System Features Unified readout boards to simplify PCB and firmware design, Each board uses a small – medium size FPGA and has it own Ethernet connection. PC side need multiple NIC to cope with multiple readout cards from one MCP, Possibility of using commercial network switch to collect multiple ethernet port in to one is to be investigated.

FPGA Function HPTDC readout control, HPTDC JTAG control, Data FIFO, Data reduction, Ethernet readout control and readout protocol implementation,

HPTDC Connection Two TDC devices, FPGA as readout controller, Shared 32-bit parallel data bus, Individual control bus for each HPTDC.

Testing Setup Optical Fibre Bottom Box Top dark box : Avalanche LED driver, 100ps pulse jitter, Fast response LED Triggering from generator Optical Fibre Bottom Box MCP, TORCH FE Boards Data transferred via ethernet, Can add active air cooling

Ethernet Readout Throughput Test to take data from 16 channels Based on Xilinx Spartan 3A Evaluation board with on-board 10/100Mbps Ethernet PHY, MAC stack implemented with Xilinx IP core (xps_ethernet_lite) PC using windows data socket for TCP/IP, wincap package for raw MAC packet capture. MAC and Lightweight IP stack with Microblaze processor: 12Mbps MAC stack only with no embedded processor: 60Mbps Conclusion: Raw MAC protocol provides adequate performance but losing the neatness of TCP/IP connection.

Firmware / Software FPGA firmware provides: Software: Raw data output for debug, Zero suppressed data output, Slow control HPTDC (via JTAG). Software: Event display, Histogram, LED triggering for testing, Temperature reading.

Torch MCP Readout Prototype. Mechanical packaging and PCB design. Three PCB flavours Stacked in a box type assembly. This is held together by two machined aluminium side plates (not currently shown in GA drawing) which contain slots for the readout cards to run in. MCP Motherboard provides Anode connectors and HV components Readout cards contain MCP anode/NINO amplifier circuits, HPTDC and FPGA devices and Ethernet transceiver hardware/connector. Clock/PSU board provides conditioned power plus synchronised global clock, and trigger signals to readout cards.

MCP motherboard Requires some final positioning to HV ladder and connector Also requires an aperture for the MCP HV wires to exit through. Will finalise the above and have the PCB made when the actual MCP device arrives and we can check our design against the real thing.

Conclusions Have real progress on packaging and PCB design, but plenty more work to do. We have experienced some delays through selection and procurement of specialist components. Cannot start spending money on PCBs until designs are finalised. Production phase will be triggered when we can inspect our MCP and confirm the fit and function of the MCP motherboard. Packaging issues give an idea of the problems to be solved re. fitment of the 8*128 pixel MCPs and electronics to Torch prism faces in the real system.