ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 13 Dr. Shi Dept. of Electrical and Computer Engineering

SEQUENTIAL CIRCUITS: LATCHES

Overview Circuits require memory to store intermediate data Sequential circuits is a circuit that has memory Flip-flop and latch Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Sequential circuits use a clock signal to determine when to store values. credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

The story so far ... Combinational circuits No way of remembering or storing information after inputs have been removed. To handle this, we need sequential logic capable of storing intermediate (or final) results.

Sequential Circuits Inputs Combinational circuit Outputs Flip Flops Next state Present state Clock Clock: a periodic external signal synchronizes when states change makes it easier to design and build large systems

Cross-coupled Inverters The system has two stable states A stable value can be stored at inverter outputs Not possible to set a desired state State 1 State 0

Cross-coupled Inverters (cont.) This circuit has no stable states

SR Latch

S-R Latch with NORs S-R latch made from cross-coupled NORs R (reset) Q S R Q Q’ 0 0 Forbidden 1 1 1 0 0 1 0 0 1 0 Set 0 1 Reset Q 0 1 Stable S (set) 1 0 S-R latch made from cross-coupled NORs If Q = 1, set state If Q = 0, reset state S=1 and R=1 generates unpredictable results reset set S R Q

S-R Latch with NORs R (reset) Q Q S (set) S R Q Q’ 0 0 Forbidden 1 1 1 1 1 0 0 1 0 0 1 0 Set 0 1 Reset Q 0 1 Stable S (set) 1 0

S-R Latch with NORs R (reset) Q S R Q Q’ 1 1 1 0 0 1 0 0 0 0 Forbidden 1 0 Set 0 1 Reset Q 0 1 Stable S (set) 1 0 What happens if both inputs R and S simultaneously change from 0 to 1? Race conditions: See who runs faster

S-R Latch with NANDs S Q Q’ R S R Q Q’ 0 0 0 1 1 0 1 1 1 1 Forbidden 0 0 0 1 1 0 1 1 1 1 Forbidden 1 0 Set 0 1 Reset 0 1 Store 1 0 Latch made from cross-coupled NANDs Sometimes called S’-R’ latch Usually S=1 and R=1 S=0 and R=0 generates unpredictable results

S-R Latches

NOR S-R Latch with Control Input Latch is level-sensitive, in regards to C Only stores data if C’ = 0 R’ Q C’ Q’ Latch operation enabled by C S’ Outputs change when C is low: RESET and SET Otherwise: HOLD Input sampling enabled by gates

S-R Latch with control input Occasionally, desirable to avoid latch changes C = 0 disables all latch state changes Control signal enables data change when C = 1 Right side of circuit same as ordinary S-R latch.

D-Latch

D Latch Q0 indicates the previous state (the previously stored value) X S D Q C Q’ R Y X Y C Q Q’ 0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ D C Q Q’

D Latch D Q C Q’ X S R Y D C Q Q’ 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ D C Q Q’ Input value D is passed to output Q when C is high Input value D is ignored when C is low

D Latch D Q C E E Latches on following edge of clock x x z z The D latch stores data indefinitely, regardless of input D values, if C = 0 Forms basic storage element in computers

Symbols for Latches SR latch is based on NOR gates S’R’ latch based on NAND gates D latch can be based on either. D latch sometimes called transparent latch

Disadvantage of Transparent Latches Problems: When G=1, D passes through the entire chair When G=1, any glitches of D passes through the entire circuit

Master-Slave D Flip Flop Consider two latches combined together Only one C value active at a time Output changes on falling edge of the clock always @(negedge clk) begin Q=D; end D C Q Q’ 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ 22

Positive and Negative Edge D Flip-Flop D flops can be triggered on positive or negative edge Bubble before Clock (C) input indicates negative edge trigger Lo-Hi edge Hi-Lo edge

Clocked D Flip-Flop Stores a value on the positive edge of C Input changes at other times have no effect on output 24

T Flip-Flop 25

Positive Edge-Triggered T Flip-Flop Created from D flop T=0 -> keep current K resets T=1 -> invert current T C Q Q’ Q0 Q0’ ­ 1 Q’0 Q0 ­

JK Flip-Flop 27

Positive Edge-Triggered J-K Flip-Flop CLK Q Q’ Created from D flop D = JQ’+K’Q J sets K resets J=K=1  invert output 0 0 Q0 Q0’ ­ 0 1 0 1 ­ 1 0 1 0 ­ 1 1 ­ TOGGLE 28

Clocked J-K Flip Flop Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output Characteristic Table 29

Asynchronous Inputs 30

Asynchronous Behavior Effects on the output are synchronized with the CLK input. Asynchronous behavior Effects on the output are synchronized with the CLK. Only used for set/reset 31

Asynchronous Inputs 32

Asynchronous Inputs Note reset signal (R) for D flip flop If R = 0, the output Q is cleared This event can occur at any time, regardless of the value of the CLK 33

Summary Flip flops are powerful storage elements They can be constructed from gates and latches! D flip flop is simplest and most widely used Asynchronous inputs allow for clearing and presetting the flip flop output Multiple flops allow for data storage The basis of computer memory! Combine storage and logic to make a computation circuit Next time: Analyzing sequential circuits. credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.