Flip Flops.

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Presentation transcript:

Flip Flops

Objectives SR latch SR Latch with enable (SR Flip-Flop) D Flip-Flop JK Flip-Flop T Flip-Flop

Flip Flop It is a type of logic circuit whose output depends not only on the present input signals but on the sequence of past inputs. A basic sequential circuit is a flip-flop Flip-flop has two stable states of output values SR Latch

2018/4/26 Flip-Flops Latches are “transparent” (= any change on the inputs is seen at the outputs immediately). This causes synchronization problems. Solution: use latches to create flip-flops that can respond (update) only on specific times (instead of any time). Types: RS flip-flop ,D flip-flop etc.

SR Latch (NAND version) 2018/4/26 SR Latch (NAND version) S’ R’ Q Q’ S’ 1 Q 0 0 0 1 1 0 1 1 1 0 Set Q’ 1 R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch (NAND version) 2018/4/26 SR Latch (NAND version) S’ R’ Q Q’ 1 S’ 1 Q 0 0 0 1 1 0 1 1 1 0 Set Q’ 1 R’ 1 0 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch (NAND version) 2018/4/26 SR Latch (NAND version) S’ R’ Q Q’ 1 S’ Q 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ R’ 1 0 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch (NAND version) 2018/4/26 SR Latch (NAND version) S’ R’ Q Q’ 1 S’ Q 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 1 R’ 1 0 Hold 0 1 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch (NAND version) 2018/4/26 SR Latch (NAND version) S’ R’ Q Q’ S’ 1 Q 1 1 Disallowed 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ R’ 1 0 Hold 0 1 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch with Enable (SR Flip-Flop) The S and R inputs only effect the output states when the enable input C is high. This controls when the latch responds to its inputs. The latch holds (stores) its value while the enable input is low — latches it! Any changes in the inputs during the time when enable is high will affect the output immediately: the circuit is said to be transparent. This circuit still has a major problem: the stored value is indeterminate if S = R = 1 when the clock goes low

D Flip-Flop The problem with S = R = 1 can be avoided using a common input D.

D Flip-Flop Qn+1 C D Q Q D Qn Qn+1 = D description Clear (reset) 1 Set Clear (reset) 1 Set input at clock output before clock output after clock Qn+1 = D A D flip-flop simply stores the value on its D input at the clock transition. The previous value stored, Qn, has no effect, unlike other flip-flops. It therefore acts as a simple memory or ‘latch’. The most widely used flip-flops: simple to build and design with. A register comprises several D flip-flops, one for each bit to be stored.

JK Flip-Flop

JK Flip-Flop Qn+1 J Q K Q J K Qn Qn+1 = J ◊ Qn + K ◊ Qn description hold 1 clear (reset) set toggle J Q K Q Qn+1 = J ◊ Qn + K ◊ Qn The excitation table for a JK flip-flop is similar to SR flip-flop but doesn’t have the problem of S = R = 1. It can perform all the operations of the simpler types of flip-flop. However, the design of the circuit internal to the flip-flop makes it more expensive to manufacture than a number of other flip-flops so JK flip-flops are now rarely used.

T-flip-flop

Toggle (T) Flip-Flop Qn+1 T Q Q T Qn Qn+1 = T ≈ Qn = T ◊ Qn + T ◊ Qn description hold 1 toggle Qn+1 = T ≈ Qn = T ◊ Qn + T ◊ Qn The output depends on the previous value stored, Qn. This type of flip-flop is rarely bought as a ‘dedicated’ device — you can easily make a T from a D flip-flop.

Thank you