The pixel research activities at SDU Jian LIU (刘剑) Shandong University liuj@hepg.sdu.edu.cn IHEP, Beijing, 27 Apr 2017

Outline Study of HV/HR CMOS sensors for the ATLAS ITk collaborating with CPPM, Marseille Research progress of the CMOS sensors for the CEPC silicon detectors and future plan Conclusion and perspectives 27/04/2017 J. LIU

HV/HR CMOS for ATLAS Phase-II Upgrade Main advantages: Commercial CMOS technology lower price per unit area. Can be thinned to tens of µm  material budget reduced. Pixel size can be reduced  improved single point resolution. 1st amplifier in-sensor  capacitively coupled to a specific digital part by gluing (compatible with ATLAS FE-I4, an readout IC for the ATLAS IBL). Explore industry standard CMOS processes as sensors: Exists in many processes, in particular HV/HR CMOS technologies, such as AMS 0.18 µm HV CMOS, GF 0.13 µm BCDlite and LF 150 nm technology, etc… Basic requirement is Deep N Well(DNW) high substrate bias voltagedriftrad-hard Triple-well technology  shielded electronics with HV. DNW: Light doping Depletion width: New large demonstrator LF CPIX was submitted on 3.2016: Pixel size 250 µm × 50 µm (FE-I4 like). Consists of three pixel flavors: passive, digital and analog pixel. Some improvements have been brought to them with respect to the characterizations of the LF CCPD prototypes. New guard-ring strategy in LF CPIX Ver2 to increase the breakdown voltage and reduce the inactive region. 27/04/2017 J. LIU

Breakdown simulation of LF CPIX V1 Top-side bias Back-side bias The DNW-pixel dominates the breakdown for both before and after irradiation. After irradiation, the BV increases from 90 V to 105 V by simulation. Fluence = 0 neq/cm2 The matrix BV is ~76 V before irradiation. The matrix BV is ~100 V at 827 MRads. 827 MRads 827 MRads after 57 days annealing Top-side bias Back-side bias Fluence = 1e15 neq/cm2 27/04/2017 J. LIU

Depletion and breakdown simulations of LF CPIX V1 and V2 Big un-depleted area between depleted edge and cutting edge  guard-ring reducing is possible  reduced dead region. V2 ~100 µm Pwellring + 2 floating guard-rings + backbias + seal-ring. The depleted region can not reach the chip edge even with removed 5 outer guard-rings. Break down voltege changed from 90 V to 170 V. 27/04/2017 J. LIU

First LF CPIX measurements T. Hirono et al (Bonn). • Breakdown occurs V1 = 130 V, V2 = 215 V. • Breakdown voltage of V2 is higher than V1, agree with the TCAD simulations! • The highest BV achieved within the ATLAS HV CMOS collaboration so far!  full depleted CMOS sensor  enhanced radiation hardness. • Simulation results will be presented in iWoRiD-2017 on July. Abstract submitted. 27/04/2017 J. LIU

HV/HR sensor test setups A test setup was developed based on the Altera DE2 board. This setup was dedicated to the sensors working in standalone mode. A test setup was developed based on the GPAC (Generic Purpose Analog Card) and the Multi-IO board, which was used for the HV/HR sensor to FE-I4 assembly test. Contributed to the board design, firmware development, data acquisition programs, in particular the programs for the proton test beam and X-ray source. Test setup in CERN PS Table IRRAD-9 in Zone-2 27/04/2017 J. LIU

The HV/HR CMOS Prototypes AMS V1 AMS V2 AMS V3 AMS V4 LF vA LF vB Prototypes characterized at CPPM: 4 AMS H18 versions (low resistivity) 1 GF 130 nm version (low resistivity) 2 LF 150 nm versions (high resistivity) GF Organized and participated in irradiation campaigns at CERN (three times at 10 keV X-ray source, three times at 24 GeV proton beam with room temperature and once at 24 GeV proton beam with -20℃) for the HV/HR CMOS prototypes. 27/04/2017 J. LIU

Prototype characterization GF HV2FEI4 assembly MPV= 1462 e- 90Sr spectrum of AMS V4, after 1 GRad X-ray irradiation. GF pixel “2”, “4” and “6” were read with weighted outputs to a single FE-I4 pixel. Performance of Radiation-hard HV/HR CMOS Sensors for the ATLAS Inner Detector Upgrades, J. Liu, et al, 2016 JINST 3 C03044 HV/HR-CMOS Sensors for the ATLAS Upgrade Concepts and Test Chip Results, J. Liu, et al, 2015 JINST 3 C03033 Threshold and noise of LF VA, after 100 MRads proton irradiation. 27/04/2017 J. LIU

Technology and prototype TowerJazz 180 nm CMOS imaging process Deep Pwell implementation 6 metal layers 15-40 µm with epi-layer 2 × 7.88 mm2 Purpose: charge collection efficiency depending on pixel dimensions & diode parameters. Submitted on 11.2015, received on 06.2016 Designed by L. Zhang 27/04/2017 J. LIU

Prototype architecture 9 blocks of pixel array Each block: 64 rows x 16 columns MINOSA-like Rolling shutter readout mode 32 µs integration time at 2 MHz clock frequency 16 parallel analog outputs 2 × 7.88 mm2 Designed by L. Zhang 3-T self biased sensor L. Zhang, et al, Investigation of CMOS pixel sensor with 0.18 µm CMOS technology for high –precision tracking detector, 2017 JINST 12 C01011 27/04/2017 J. LIU

Test setup development SE: Single Ended DUT Main Board Xilinx FPGA board PC SE SE PCIe LVDS LVDS RS232 SSD Sketch of the test setup for CMOS sensor test External power Oscilloscope The test setup consists of, DUT board: carry the chip, bias the chip, buffer the output Main board (designed by IHEP): supply the power to the chip, sample the output signals, etc… FPGA board: communicate with PC via PCIe, control the data loading/receiving SSD high speed data store  >1Gb/s. Could support both the vertex pixels and the tracker pixels. 27/04/2017 J. LIU

DUT board DUT PCB layout Wire-bonding diagram Diode bias Analog external Power connector Digital external Diode bias chip Digital block Analog block Connector to main board DUT Wire-bonding diagram 27/04/2017 J. LIU

Verification test of the DUT board output input Amplifier Gain = 2 Level shifter Amplifier Gain = 1 input Both the analog block and digital block worked as expected. Minor modifications have been done in v2. Sent to bonding company this week. output 27/04/2017 J. LIU

Firmware & software design Microblaze soft-core KC 705 The test setup is based on the Xilinx KC705 board Kintex 7 FPGA  Microblaze (configure the chip) + xillybus (PCIe data transformation). Software is based on Qt and ROOT  GUI for user. Qt GUI Xillybus IP 27/04/2017 J. LIU

What we have done by using TCAD DC: Breakdown voltage in the critical region. AC: Input capacitance from the Pwell and DNW. Cpw-dnw Cinter Cdnw DC: Depletion evaluation depending on the biasing voltage and the resistivity. DC: Leakage current. Transient: Charge collection behavior. DC, AC and transient simulations were performed taking into account both the TID and NIEL effects. 27/04/2017 J. LIU

Simulation overview for TJ 180 nm technology Layout Epi-layer resistivity 1 kohm.cm Epi-layer thickness 18 um Substrate resistivity 10 ohm.cm Substrate thickness 200 um 3D devices 27/04/2017 J. LIU

Depletion Depletion depth The contour in white: depletion edge. The depletion depth is ~ 6 um @ HV = -3.3V 27/04/2017 J. LIU

Breakdown (1/2) Leakage current vs. HV F: F11_S8 F50_S20 BV @ o neq/cm2 (-V) 15 42 BV @ 1e14 neq/cm2 (-V) 14 43 The breakdown voltages are not influenced obviously after 1e14 neq/cm2. 27/04/2017 J. LIU

Breakdown (2/2) E-field of F11_S8 F50_S20 has better breakdown voltage due to the large distance between the NW and the PW, which results in lower e-field around the junction region. E-field of F50_S20 27/04/2017 J. LIU

Pixel capacitance (1/2) Capacitance vs. HV The NW capacitance of the six pixel flavors were simulated through AC simulation. 27/04/2017 J. LIU

Pixel capacitance (2/2) F5_S4 F11_S8 F15_S6 F18_S12 F44_S20 F50_S20 Gap (um) 0.25 0.39 0.91 0.55 1.3 1.55 Cap (fF)@ HV = -3.3V 5.7 6.1 3.4 6.6 5.2 4.6 The lateral capacitance has significant contribution to the total capacitance due to the narrow gap. Increased gap distance would reduce the capacitance and increase the breakdown voltage significantly. Gap: the gap between the PW and the NW 27/04/2017 J. LIU

Transient simulation overview Focused in this talk F11_S8 with pitch of 21 um in X and 21 um in Y F11_S8 with pitch of 21 um in X and 42 um in Y 3 different pitches for the pixel “F11_S8” were simulated. The MIP particle impinging direction is perpendicular to the device surface. F11_S8 with staggered pitch of 21 um in X and 84 um in Y MIP impinging 27/04/2017 J. LIU

Transient simulation (1/6) A E-field barrier exits due to the doping difference between the epi-layer and substrates  act as a mirror for the diffusion electrons and holes. E-field along Z-axis 27/04/2017 J. LIU

Transient simulation (2/6) Electron current density vs. time Hole current density vs. time 27/04/2017 J. LIU

Transient simulation (3/6) Pixel 17 Pixel 13. Impinging position. Pixel 12 Responses for the MIP impinging drift charges Induced bipolar pulses. diffusion charges. Diffusion charges lost due to radiation effects. 27/04/2017 J. LIU

Transient simulation (4/6) Pixel 17. 50% charges survived after 1e14 neq/cm2 for Pixel 13. No charge collection after 1e14 neq/cm2 for Pixel 12 and Pixel 17. Pixel 13. Impinging position. Pixel 12. 27/04/2017 J. LIU

Transient simulation (5/6) Impinging position Pixel 13 Responses for the MIP impinging Charge collection dominated by diffusion. 27/04/2017 J. LIU

Transient simulation (6/6) Impinging position Pixel 13. Almost No charge collection after 1e14 neq/cm2 for Pixel 13. Sensor can not withstand radiation level > 1e14 neq/cm2. Full depletion needed in X direction  >99% fill factor  larger diode size, HV, HR, etc… Y X 27/04/2017 J. LIU

Conclusion and perspectives ATLAS: Seven prototypes have been characterized. Radiation harness to 100 MRads and 1015 neqcm-2  an option for the HL-LHC. TDR by the end of 2017. The TCAD simulations of the CMOS sensors show good agreement with the measurements. Expected improvements have been observed from the preliminary tests. Continue to collaborate with CPPM for the HV/HR sensor study. CEPC: A test setup based on Xilinx Kintex-7 FPGA is under developing. Could support both the vertex and tracker pixels. TCAD simulations for the TJ 180 nm technology have been performed. Both the DC, AC and transient properties were explored. The current sensor layout might not work for the CEPC vertex detector. The PCBs have been designed and are under testing. The firmware and software developments are in process. First data taking will be in summer. New pixel geometries for both the vertex and tracker cases will be simulated carefully  try to achieve >99% fill factor after 1e14 neq/cm2. HV/HR technology investigation is ongoing for the CEPC vertex and tracker. Preparing the next MPW run for the CEPC pixelated silicon tracker and radiation damage study. Thank you! 谢谢！ 27/04/2017 J. LIU