Fault Tree Analysis Using Binary Decision Diagrams

Slides:



Advertisements
Similar presentations
Switching circuits Composed of switching elements called “gates” that implement logical blocks or switching expressions Positive logic convention (active.
Advertisements

Digital Logic Design Gate-Level Minimization
Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection
1 Combinational Logic Design&Analysis. 2 Introduction We have learned all the prerequisite material: – Truth tables and Boolean expressions describe functions.
1 Fault-Tolerant Computing Systems #6 Network Reliability Pattara Leelaprute Computer Engineering Department Kasetsart University
CSE 322: Software Reliability Engineering Topics covered: Dependability concepts Dependability models.
Safety Analysis – A quick introduction RTS February 2006 Anders P. Ravn Aalborg University.
Chapter 4 Logic Gates and Boolean Algebra. Introduction Logic gates are the actual physical implementations of the logical operators. These gates form.
 2000 M. CiesielskiPTL Synthesis1 Synthesis for Pass Transistor Logic Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts,
Title slide PIPELINE QRA SEMINAR. PIPELINE RISK ASSESSMENT INTRODUCTION TO RISK IDENTIFICATION 2.
ENGG 1203 Tutorial Combinational Logic (I) 1 Feb Learning Objectives
In this module you will learn: What the various logic gates do. How to represent logic gates on a circuit diagram. The truth tables for the logic gates.
What is Fault Tree Analysis?
FaultTree+ V11 Summary of Fault and Event Tree Methods
CS1Q Computer Systems Lecture 5 Simon Gay. Lecture 5CS1Q Computer Systems - Simon Gay2 Where we are Global computing: the Internet Networks and distributed.
Module 3.  Binary logic consists of :  logic variables  designated by alphabet letters, e.g. A, B, C… x, y, z, etc.  have ONLY 2 possible values:
1 Fundamentals of Computer Science Propositional Logic (Boolean Algebra)
Logic Design A Review. Binary numbers Binary numbers to decimal  Binary 2 decimal  Decimal 2 binary.
Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part I.
1 Boolean Algebra & Logic Gates. 2 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple.
FAULT TREE ANALYSIS (FTA). QUANTITATIVE RISK ANALYSIS Some of the commonly used quantitative risk assessment methods are; 1.Fault tree analysis (FTA)
RLV Reliability Analysis Guidelines Terry Hardy AST-300/Systems Engineering and Training Division October 26, 2004.
Functional Modeling.
4-3 Addition Rule This section presents the addition rule as a device for finding probabilities that can be expressed as P(A or B), the probability that.
Pattara Leelaprute Computer Engineering Department
Stracener_EMIS 7305/5305_Spr08_ System Reliability Analysis - Multi State Models and General Configurations Dr. Jerrell T. Stracener, SAE Fellow.
Prof. Enrico Zio Fault tree analysis Prof. Enrico Zio Politecnico di Milano Dipartimento di Energia.
Fault Tree Analysis for the BLEDP Student meeting Vegard Joa Moseng.
Introduction to GO-FLOW Method and Comparison to RGGG Method Lab Seminar Dec. 13th, 2010 Seung Ki Shin.
Process of Diagnosing a Dynamic System Lab Seminar June 19th, 2007 Seung Ki Shin.
A fault tree – Based Bayesian network construction for the failure rate assessment of a complex system 46th ESReDA Seminar May 29-30, 2014, Politecnico.
Verification vs. Validation Verification: "Are we building the product right?" The software should conform to its specification.The software should conform.
LOGO Combining Fault Trees and Event Trees Seung Ki, Shin.
Adding Dynamic Nodes to Reliability Graph with General Gates using Discrete-Time Method Lab Seminar Mar. 12th, 2007 Seung Ki, Shin.
Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經 察政章(Chapter 58) 伏者潛藏也
Notes Over 1.2.
Boolean Algebra & Logic Gates
Digital Logic.
Truth Table to Statement Form
CHAPTER 7 MULTI-LEVEL GATE CIRCUITS / NAND AND NOR GATES
CHAPTER 3 Simplification of Boolean Functions
Fault Trees.
Department of Preparatory Year, Umm Al Qura University
NAND as a complete system and Karnaugh Maps
Eng. Mai Z. Alyazji October, 2016
Logic Gates and Boolean Algebra
Combinational Logic Design&Analysis.
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
Business Modeling Lecturer: Ing. Martina Hanová, PhD.
VLSI Testing Lecture 5: Logic Simulation
Fault Tree Analysis Based on Dynamic Uncertain Causality Graph
ECE 3110: Introduction to Digital Systems
Digital Logic.
Component 1 – 2A, B, C Binary Logic
Reading: Hambley Chapters
Circuits, Truth Tables & Boolean Algebra
Circuit Design Process
CSE 370 – Winter Combinational Implementation - 1
Boolean Logic Boolean Logic is considered to be the basic of digital electronics. We know that a computer’s most basic operation is based on digital electronics.
Logic Gates.
Formal Methods in software development
Circuit Design Process
GCSE Computer Science – Logic Gates & Boolean Expressions
Formal Methods in software development
Dr. Clincy Professor of CS
A logic function f in n inputs x1, x2, ...xn and
A logic function f in n inputs x1, x2, ...xn and
Copyright © Cengage Learning. All rights reserved.
Digital Logic Design Basics Combinational Circuits Sequential Circuits.
Presentation transcript:

Fault Tree Analysis Using Binary Decision Diagrams Lab Seminar May 4th, 2006 Seung Ki, Shin

Contents Introduction Classification of Fault Trees Shortcoming of Conventional Fault Tree Analysis Binary Decision Diagrams Approach Example of Non-Coherent Fault Tree Summary & Further Study References

Introduction The fault tree diagram itself is an excellent way of deriving the failure logic for a system. Conventional fault tree analysis techniques have several disadvantages when analyzing some kinds of fault trees. It is possible to overcome these disadvantages using Binary Decision Diagram (BDD) method.

Classification of Fault Trees Static Coherent Non-coherent Dynamic Static fault tree : Composed of Boolean gates Dynamic fault tree : Adding sequential notion to static fault tree

Classification of Fault Trees Coherent fault tree Logical gates are restricted to AND and OR gates. Top event is described in terms of Minimal Cut Sets. Minimal Cut Set : Combination of component failure events which are necessary and sufficient to cause the top event. ex) Non-coherent fault tree Inverse gates besides AND and OR gates. (NOT, NAND, NOR, and XOR gates) Top event is described with Prime Implicants from Boolean algebra. Prime Implicant : Combination of basic events (success or failure) which is both necessary and sufficient to cause the top event.

Shortcoming of Conventional Fault Tree Analysis Inclusion-Exclusion Expansion (IEE) ( are minimal cut sets/prime implicants ) For complex systems an analysis may produce hundreds of thousands of minimal cut sets. Then it is impossible to calculate the exact probability using IEE. Truncation of the expansion is used to simplify the calculation. It is justified for coherent fault trees. For non-coherent fault trees, this approximation is not valid and creates considerable inaccuracies in evaluating top event probability.

Shortcoming of Conventional Fault Tree Analysis The prime implicants are frequently reduced to their coherent approximations by assuming any working states for the components in the expression are set to TRUE. This approximation may induce considerable inaccuracies.

Binary Decision Diagrams Approach The binary decision diagram (BDD) method was utilized by Bryant and later developed by Rauzy. BDD provides an alternative logic form to the fault tree structure to express the system failure causes. Exact system failure probability can be deduced without the need to resort to any approximations. The BDD structure has the additional advantage that its quantification does not require the minimal cut sets/prime implicants.

Binary Decision Diagrams Approach 1 Terminal Node <Fault Tree> <Binary Decision Diagram>

Binary Decision Diagrams Approach Conventional Method Minimal Cut Sets : Probability of Top Event (Inclusion-Exclusion Expansion) Binary Decision Diagrams Approach Disjoint Path : Probability of Top Event * Due to the binary branching each path in the BDD is mutually exclusive and so the probability of system failure is obtained by simply summing the probability of each disjoint path leading to a terminal one node.

Example of Non-Coherent Fault Tree - Each component failure probability : 0.1

Example of Non-Coherent Fault Tree Exact Calculation Using IEE Method Min cut set : Probability of top event : 0.094851 Two Conventional Approximations Truncation (after one term) Coherent approximation Min cut set becomes Very inaccurate !

Example of Non-Coherent Fault Tree Binary Decision Diagram Approach 1 Disjoint Path Probability 0.00729 0.006561 0.081 Total 0.094851 Simple & Exact !

Summary & Further Study When analyzing non-coherent systems, it is shown that analysis methods based on traditional fault tree analysis are both inaccurate and inefficient. It has been shown that analysis procedures based on binary decision diagrams to represent the system failure logic can produce all minimal cut sets for problems which defeat conventional approaches. The size of the resulting BDD is determined by the ordering that has to be given to the basic events in the fault tree before the BDD is constructed. To improve the efficiency of the BDD analysis, it is important to seek a BDD of minimal size when a certain fault tree is given.

References J.D. Andrews, S.J. Dunnett, “Event Tree Analysis Using Binary Decision Diagrams”, IEEE, 2000. A. Rauzy, “New algorithms for fault trees analysis”, Reliability Engineering and System Safety, 1993. R.M. Sinnamon, J.D. Andrews, “Improved Efficiency in Qualitative Fault Tree Analysis”, Quality and Reliability Engineering International, 1997.