Nanoscale Power Delivery & PI Raj Nair, Anasim Corp. Aug. 21, 2013 (Updated) Overview The Power Integrity (PI) Wall PI Analysis Management & Innovation Potential Publications & Discussion

Power Integrity & the PI Wall PI degradation with scaling* ~= For constant power density (CPD) or constant power (CP) scaling, where k is the process scaling factor, typically 0.7 Classical CPD/CP scaling → ~70% degradation in PI 20nm SoC to 16nm FinFET transition Appears Constant Power and Constant Power Density, higher cost ~40% PI degradation; with k = 0.8 and the inverse k-root-k metric 16nm to 10nm Scale factor 0.625, leads to > 2X (> 100%) degradation in PI!! We have seen PI-related product failures (FMAX, INRUSH I) in the past and the present. Business as usual NOT an option. 08/21/13 Anasim Confidential * “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010

PI analysis prior art (Droop, IR Drop) Lumped and Polygonal  Not True-Physical and Spatio-Temporal, eliminates spatial variance and temporal coincidence Not wideband, and leads to pessimistic, non-optimal chip/pkg/board design. Loses local resonances, constructive/destructive noise interference 08/21/13 Anasim Confidential

Differential¹ modeling & design Grids, transmission lines/planes Abstract, system level, continuous² No freq/time domain discontinuities 08/21/13 Anasim Confidential ¹ Integrity learning from the SI world and from fundamentals ² “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010

PI: How do droops REALLY look? Supply differential True-physical power grid noise (π-fp); droops and propagation 08/21/13 Anasim Confidential

Continuum³ analysis insight True-physical noise wave propagation (rlcsim) 08/21/13 Anasim Confidential ³ “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI

PI mngmnt: Fundamental methods On-die capacitance Quantity Type (fixed/variable) Degradation in deep nanoscale (Q, leak) Placement and distribution ~130nm process 0.0E+00 2.0E-07 4.0E-07 6.0E-07 8.0E-07 1.0E-06 1.2E-06 1.4E-06 1.6E-06 -2 -1 1 2 Vg [V] C [f/cm^2) 3 1.5 1 nS A 100 V V= 50mV VCC Can a fine-grain distribution of de-coupling capacitors minimize the di/dt problem? 08/21/13 Anasim Confidential

PI management: Power Grid Design Differential grid architecture Novel simulation algo. & IP* What-if analysis in minutes... 08/21/13 Anasim Confidential * “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010

PI management: Power Grid Sims 08/21/13 Anasim Confidential Anasim Corp., Power Integrity Aware Methodology

PI Management: Package Cap Loop-L4 Load-shift induced noise Transient & DC Package dependency Scaling challenge Exponent of scale factor Pkg. caps help, but... 08/21/13 Anasim Confidential 4 “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI

PI management: Fast Regulation Simulation (0.18μm) Idealized parasitics 4:1 ESL ratio between grids Capacitance evenly distributed N-Series-Pass Inherently stable Fast response Charge Valve benefits ~25% VCC droop reduction in sim Apparently kicks in within 50pS Sub-50pS response 65mV droop 88mV droop LVDCAP and HVDCAP were 5pF each in the active configuration and 10pF, 0pF in the inactive mode. 08/21/13 Anasim Confidential Raj Nair, “Distributed charge Valves”, research conducted in late 1999 at Intel Labs, Oregon

PI mngmnt: Active Noise Regulation* Tested in lumped (b/w) and continuum (π-fp) model simulations 08/21/13 Anasim Confidential *Raj Nair, “Active Noise Regulators”, US Patent 7291896,http://www.anasim.com/active-noise-regulation/

Distributed Local Voltage Regulation5 Split, distribute lumped regulator components Switches Inductors, CAPs Reducing IL per branch Increases Bandwidth LC α (1/f2) Reducing CAP need And Efficiency I2R losses reduced significantly (ind.) Modular design Flexible form factor Distributes power and heat dissipation Transient-suppressing high-BW regulation6 08/21/13 Anasim Confidential 6 Nair, US patent appl. pub. US 2005/0168890 A1, filed Jan. 24, 2004 5 “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI

PI mngmnt. innovation opportunities Board, package, and chip-level Regulation, form-factor dependent Hybrid regulation Active noise regulation Distributed voltage regulation Integration (on-die, on-pkg...) Tools & Methodology (Architecture, Design, Verification...) References Power Integrity Analysis and Management for Integrated Circuits Raj Nair & Donald Bennett Prentice-Hall, Publication Date: May 17, 2010 | ISBN-10: 0137011229 | ISBN-13: 978-0137011223 | Edition: 1 http://www.amazon.com/Integrity-Analysis-Management-Integrated-Circuits/dp/0137011229/ Power Integrity for Nanoscale Integrated Systems Masanori Hashimoto & Raj Nair McGraw-Hill, Publication Date: February 26, 2014 | ISBN-10: 0071787763 | ISBN-13: 978-0071787765 | Edition: 1 http://www.amazon.com/Power-Integrity-Nanoscale-Integrated-Systems/dp/0071787763/ 08/21/13 Anasim Confidential

Backup slides 08/21/13 Anasim Confidential

Lumped simulation model with ANR 08/21/13 Anasim Confidential

PRESCOTT Pre-ANR 08/21/13 Anasim Confidential

PRESCOTT Post-ANR 08/21/13 Anasim Confidential