Chapter2 ARM 프로세서를 이용한 SoC설계 구조 이해 2.1 ARM926 Processor 2.2 Memory system 2.3 High speed connectivity 2.4 Low speed connectivity 2.5 ARM926 Block Diagram 2.6 Memory Map

2.0 ARM9 Microprocessor % RISC와의 비교 RISC에서 채택한 기능 Load Store 구조 Fixed Length 32 bit 3 register instruction format RISC에서 채택하지 않은 기능 Register Windows Delayed Branch Single-cycle execution % 아키텍쳐 ARM7 : Fetch-Decode-Execute 3-stage pipeline ARM9 : Fetch-Decode-Execute-Data-Write Back 5-stage pipeline

2.0 ARM Implementation Data Path (Full Custom Design) Adder : 초기 : Ripple Carry Adder ARM2 : 4-bit Carry Look Ahead Adder(CLA) ARM6 : Carry Select Adder ARM9 : Carry Arbitration Adder (parallel-prefix tree를 이용하여 중간 carry 계산) Barrel Shifter Multiplier Carry Propagate Adder Carry Save Adder Register Bank Control Path (Synthesis) Main decoder : PLA

2.1 ARM926 Processor EasySoC ARM926EJ-S Processor 개요 프로세서 Features 110nm 공정의 HCMOS 기술로 이루어진 시스템 온 칩 AMBA AHB에 대한 Pin 입/출력이 가능하도록 설계 사용자가 설계한 IP를 AMBA AHB에 연결할 수 있음 프로세서 Features CPU ARM926EJ-S RISC Processor fMAX 266 MHz (downward scalable) Virtual address support with MMU 32 KB instruction CACHE (4 way set associative) 16 KB data CACHE (4 way set associative) 8 KB instruction TCM 8 KB data TCM Coprocessor interface JTAG ETM9 (rev 2.2), large size FIFO Internal bus structures Multilayer structure AMBA 2.0 compliant fMAX 133 MHz High speed I/Os with embedded DMA function Clock system Programmable clock generator PLL with E.M.I. reduction Low Jitter PLL for USB 2.0

2.2 Memory system Interrupt controller Memory on chip IRQ and FIQ interrupt generations Support up to 32 standard interrupts Support up to 16 vectored interrupts Software interrupt generation Memory on chip 16 KBytes single-port SRAM embedded in the eASIC™MacroCell. It can be used on AHB Bus or directly by the custom logic. SPI (Serial Peripheral Interface) 4 chip selects for asynchronous devices (ROM, Flash) Supports Normal mode 20 MHz and Fast mode 50 MHz AHB slave Accessible memory: 64 MB 8 / 16 / 32 bit widths Programmable wait states Multi-port memory controller Maximum clock frequency 133 MHz Support up to 7 AHB master requests Support for 8, 16 and 32 bit wide SDRAM Support for 8 and 16 bit wide DDR 4 chip selects Physical addressable memory up to 256 MB Memory clock tuning to match the timing of different memory vendors

2.3 High speed connectivity USB 2.0 host 2 USB 2.0 Host controllers with their UTMI PHY port embedded High-Speed / Full-Speed / Low-Speed modes USB 2.0 complaint DMA FIFO 2 AHB slaves for configuration and FIFO access 2 AHB masters for data transfer USB 2.0 device UDC 2.0 controller with embedded PHY USB Self-Power mode Master interface for DMA transfer to DRAM memory AHB slaves for: configuration, FIFO access, Plug autodetect Endpoints on the top of endpoint 0: 3 bulkin / bulkout, 2 isochronous Ethernet 10/100 MAC110 controller compliant with IEEE 802.3 standard Supporting MII 10/100 Mbits/s MII management protocol interface TX FIFO (512x36 Dual Port) RX FIFO (512x36 Dual Port) AHB slave for configuration

2.4 Low speed connectivity UART Support for 8 bit serial data TX and RX Selectable 2 / 1 Stop bits Selectable Even, Odd and No Parity Parity, Overrun and Framing Error detector Max transfer rate : 115 Kbps I2C Standard I2C mode (100 KHz) / Fast I2C mode (400 KHz) Master interface only Master functions control all I2C bus specific sequencing, protocol, arbitration and timing Detection of bus errors during transfers General purpose I/Os : 6 programmable GP I/Os Real time clock Real time clock-calendar (RTC) 14 digit (YYYY MM DD hh mm ss) precision Clocked by 32.768 KHz low power clock input Separated power supply (1.2 V)

General purpose timers Watchdog timer Programmable 16 bit Watchdog timer with reset output signal (more than 200 system clock period to initial peripheral devices) Programmable period 1 ~ 10 sec. For recovery from unexpected system Hang-up General purpose timers Four 16 bit timers with 8 bit prescaler Frequency range : 3.96 Hz - 66.5 MHz Operating mode : Auto Reload and Single Shot Customizable logic 200K equivalent ASIC gate (16K LUT equivalent) configurable either custom logic or 32KBytes single-port SRAM or mixing logic and RAM 2 dedicated buses, each of them connected with a 4 channel DMA 8 interrupt lines (level type) available 112 dedicated GP I/Os Single VIA mask configurable interconnections Emulation by an external FPGA, keeping on-chip and I/O interfaces

2.5 ARM926 Block Diagram

2.6 Memory Map START ADRESS END ADDRESS PERIPHERAL NOTES 0x0000_0000 0x03FF_FFFF Serial Memory 64 MB (on reset before the remap) 0x0FFF_FFFF DRAM 256 MB 0x1000_0000 0x1000_07FF USB Device 0x1000_8000 0x1000_8FFF USB Device Plug Detect 0x1000_9000 0x1000_9FFF USB Host 1 EHCI 0x1000_A000 0x1000_AFFF USB Host 1 OHCI 0x1000_B000 0x1000_BFFF Vectored Interrupt CTRL 0x1000_C000 0x1000_CFFF DRAM CTRL (MPMC) 0x1000_D000 0x1000_DFFF USB Host 2 EHCI 0x1000_E000 0x1000_EFFF USB Host 2 OHCI 0x1000_F000 0x1000_F3FF Serial Memory CTRL 0x1000_F400 0x11FF_FFFF Default Slave 0x1200_0000 0x1200_0FFF APB Control Status Register 0x1200_1000 0x1200_1FFF GPT 0 and GPT 1 0x1200_2000 0x1200_2FFF GPT 2 and GPT 3 0x1200_3000 0x1200_3FFF General Configuration Registers 0x1200_4000 0x1200_4FFF WdT 0x1200_5000 0x1200_5FFF RTC 0x1200_6000 0x1200_6FFF GPIO 0 → GPIO 5

eASIC™ Programmable Interface 0x1300_0400 0x13FF_FFFF 0x1400_0000 START ADRESS END ADDRESS PERIPHERAL NOTES 0x1200_7000 0x1200_7FFF I²C 0x1200_8000 0x1200_8FFF UART 1 0x1200_9000 0x1200_9FFF UART 2 0x1200_A000 0x1200_AFFF UART 3 0x1200_B000 0x1200_BFFF ADC 0x1200_C000 0x1200_CFFF gDMA 1 0x1200_D000 0x1200_DFFF gDMA 2 0x1200_E000 0x120F_FFFF Default Slave 0x1210_0000 0x12FF_FFFF 0x1300_0000 0x1300_03FF eASIC™ Programmable Interface 0x1300_0400 0x13FF_FFFF 0x1400_0000 0x15FF_FFFF Ethernet MAC 0x1600_0000 0x19FF_FFFF Serial Memory 64 MB (on reset after the remap) 0x1A00_0000 0x1FFF_FFFF (maximum addressable size available for the set of the full master and the 2 slaves is 1.5 GB) 0x2000_0000 0x7FFF_FFFF eASIC™ AHB SUBSYSTEM