Gruppo Server CCR michele.michelotto at pd.infn.it Status Report

michele michelotto - INFN Padova All_cpp SPECint2006 (12 applications) Well established, published values available HEP applications are mostly integer calculations Correlations with experiment applications shown to be fine SPECfp2006 (17 applications) SPECall_cpp2006 (7 applications) Exactly as easy to run as is SPECint2006 or SPECfp2006 No published values (not necessarily a drawback) Takes about 6 h (SPECint2006 or SPECfp2006 are about 24 h) Best modelling of FP contribution to HEP applications Important memory footprint Proposal to WLCG to adopt SPECall_cpp 2006, in parallel and call it HEP SPEC06 CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova SPEC CPP 471.omnetpp 473.astar 483.xalancbmk 444.amd 447.dealII 450.soplex 453.povray Integer tests Floating Point tests CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova ccp_all on FP CCR 03/09 michele michelotto - INFN Padova

Relative performances CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Hep-Spec06 Machine SPEC2000 SPEC2006 int 32 SPEC2006 fp 32 SPEC2006 CPP 32 lxbench01 1501 11.06 9.5 10.24 lxbench02 1495 10.09 7.7 9.63 lxbench03 4133 28.76 25.23 28.03 lxbench04 5675 36.77 27.85 35.28 lxbench05 6181 39.39 29.72 38.21 lxbench06 4569 31.44 27.82 31.67 lxbench07 9462 60.89 43.47 57.52 lxbench08 10556 64.78 46.48 60.76 CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Conversion factor Choose an approssimate conversion factor (~5%) Giving more weight to modern processor We choose “4” to stress that we don’t care precision but easiness of portability To validate we measured the whole GridKa and found it ok CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova More cpu CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova CPU Outlook Intel Xeon Harpertown 54xx AMD Opteron Shanghai Intel Xeon Nehalem 55xx CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Harpertwon Cache L1 32+32KB Cache L2 3MB/core Xeon 5420: 2.0 Ghz  Xeon 5460: 3.3 GHZ FSB 1333 MHz Xeon 5472: 3.0 Ghz  Xeon 5492: 3.4 GHZ FSB: 1666 MHz CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Shanghai Opterpn 2376 2.3 GHz  2384SE 2.7 GHz 45 nm process: 75W SE 105W 2.8 Ghz HE 2344 1.7GHz  HE2376 2.3 GHz Cache L1 64+64 KB Cache L2 0.5MB/core Cache L3 6MB shared (cfr. 2MB Barcelona) CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Nehalem “gainestown” 45 nm Cache L1 32+32 KB Cache L2 256KB/core Cache L3 3MB shared 80W: E5502 1.86 GHz  E5540 2.53 GHz 95W: X5550 2.66 GHz  X5570 2.93 GHz 29 Marzo 2009? Dual Thread, Turbo Mode CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Nehalem: 3 DDR3 channels per socket Opteron 2 DDR2 channel Harpertown Through Front Side Bus CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Nehalem memory The standard Worker node 2 socket, 4 core per socket, 2GB per core  We specify 16 GB total memory per WN Nehalem 6 or 12/18 memory slot (at least 6 slots filled?) 2, 4 or 8 GB per core Total memory: 12, 24 or 48 GB Do we need to double memory to run two thread per core? CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova Core i7 Single processor, 4 core, 8 logical cpu with Thread enabled 8 MB L3 cache 920 2.66 GHz  975 3.33 GHz Back to single socket WN? CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova 1 Corei7 vs 2x2384 CCR 03/09 michele michelotto - INFN Padova

michele michelotto - INFN Padova CCR 03/09 michele michelotto - INFN Padova