Topics Coarse-grained FPGAs. Reconfigurable systems.

Slides:

Advertisements

Similar presentations

Field Programmable Gate Array

Advertisements

FPGA (Field Programmable Gate Array)

Commercial FPGAs: Altera Stratix Family Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

Reconfigurable Computing (EN2911X, Fall07) Lecture 04: Programmable Logic Technology (2/3) Prof. Sherief Reda Division of Engineering, Brown University.

TIE Extensions for Cryptographic Acceleration Charles-Henri Gros Alan Keefer Ankur Singla.

Class Presentation Of Advance VLSI Course Presented by : Ali Shahabi Major Refrence is : Architecture and Circuit Techniques for a Reconfigurable Memory.

The Microprocessor is no more General Purpose. Design Gap.

A Survey of Logic Block Architectures For Digital Signal Processing Applications.

Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.

Floating-Point FPGA (FPFPGA) Architecture and Modeling (A paper review) Jason Luu ECE University of Toronto Oct 27, 2009.

Hardwired networks on chip for FPGAs and their applications

EECE579: Digital Design Flows

PipeRench: A Coprocessor for Streaming Multimedia Acceleration Seth Goldstein, Herman Schmit et al. Carnegie Mellon University.

Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What.

Programmable logic and FPGA

February 4, 2002 John Wawrzynek

CS 151 Digital Systems Design Lecture 38 Programmable Logic.

Introduction to FPGA and DSPs Joe College, Chris Doyle, Ann Marie Rynning.

1 A survey on Reconfigurable Computing for Signal Processing Applications Anne Pratoomtong Spring2002.

Paper Review I Coarse Grained Reconfigurable Arrays Presented By: Matthew Mayhew I.D.# ENG*6530 Tues, June, 10,

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture.

A RISC ARCHITECTURE EXTENDED BY AN EFFICIENT TIGHTLY COUPLED RECONFIGURABLE UNIT Nikolaos Vassiliadis N. Kavvadias, G. Theodoridis, S. Nikolaidis Section.

J. Christiansen, CERN - EP/MIC

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR FPGA Fabric n Elements of an FPGA fabric –Logic element –Placement –Wiring –I/O.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

Embedded Runtime Reconfigurable Nodes for wireless sensor networks applications Chris Morales Kaz Onishi 1.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Overview n Why VLSI? n Moore’s Law. n Why FPGAs? n The VLSI and system design process.

Field Programmable Gate Arrays (FPGAs) An Enabling Technology.

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture.

Lecture 16: Reconfigurable Computing Applications November 3, 2004 ECE 697F Reconfigurable Computing Lecture 16 Reconfigurable Computing Applications.

EE3A1 Computer Hardware and Digital Design

Overview Why VLSI? Moore’s Law. Why FPGAs? Circuit Component

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Reconfigurable Architectures Forces that drive.

COARSE GRAINED RECONFIGURABLE ARCHITECTURES 04/18/2014 Aditi Sharma Dhiraj Chaudhary Pruthvi Gowda Rachana Raj Sunku DAY

Modeling Mobile-Agent-based Collaborative Processing in Sensor Networks Using Generalized Stochastic Petri Nets Hongtao Du, Hairong Qi, Gregory Peterson.

Computer Architecture SIMD Ola Flygt Växjö University

Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability Pascal BENOIT G. Sassatelli – L. Torres – D. Demigny M. Robert – G.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Moore’s Law n Gordon Moore: co-founder of Intel. n Predicted that number of transistors.

Survey of multicore architectures Marko Bertogna Scuola Superiore S.Anna, ReTiS Lab, Pisa, Italy.

Reconfigurable architectures ESE 566. Outline Static and Dynamic Configurable Systems –Static SPYDER, RENCO –Dynamic FIREFLY, BIOWATCH PipeRench: Reconfigurable.

1 Advanced Digital Design Reconfigurable Logic by A. Steininger and M. Delvai Vienna University of Technology.

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

System on a Programmable Chip (System on a Reprogrammable Chip)

Reconfigurable Computing1 Reconfigurable Computing Part II.

Reconfigurable Computing - Performance Issues John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound, Western.

Programmable Hardware: Hardware or Software?

Jotham Vaddaboina Manoranjan, Kenneth S. Stevens

Reconfigurable Architectures

Floating-Point FPGA (FPFPGA)

Altera Stratix II FPGA Architecture

Topics SRAM-based FPGA fabrics: Xilinx. Altera..

ECE354 Embedded Systems Introduction C Andras Moritz.

Instructor: Dr. Phillip Jones

Introduction to Reconfigurable Computing

Anne Pratoomtong ECE734, Spring2002

Lecture 41: Introduction to Reconfigurable Computing

Hyunchul Park, Kevin Fan, Manjunath Kudlur,Scott Mahlke

Overview Why VLSI? Moore’s Law. Why FPGAs?

Characteristics of Reconfigurable Hardware

HIGH LEVEL SYNTHESIS.

A small SOPC-based aircraft autopilot system that contains an FPGA with a Nios processor core, a DSP processor, and memory is seen above. The bottom sensor.

A SRAM-based Architecture for Trie-based IP Lookup Using FPGA

Physical Implementation

The University of Adelaide, School of Computer Science

Programmable logic and FPGA

Reconfigurable Computing (EN2911X, Fall07)

Overview Why VLSI? Moore’s Law. Why FPGAs?

Presentation transcript:

Topics Coarse-grained FPGAs. Reconfigurable systems. Reconfigurable ASICs.

FPGA granularity Typical LEs implement a small amount of logic. Waste a lot of space/power on connecting logic elements. Specialized adder logic tries to solve this problem for a special case. Can build FPGAs with larger elements.

Granularity issues How big is the logic element? How flexible should it be? What interconnection network is needed? How do you program it?

Reconfigurable systems Reconfigure logic on-the-fly: application characteristics may change over time. Issues: Reconfiguration time. Reconfiguration memory cost. Power consumption. Synthesis for reconfiguration.

PipeRench Reconfigurable pipeline: Each stage of the pipeline can be reconfigured quickly and independently. Allows virtual pipeline that is longer than physical pipeline.

PipeRench pipeline operation

RaPiD architecture Coarse-grained computational architecture: Soft control can be reconfigured on every cycle. Hard control can be reconfigured only in configuration mode. Interconnect network allows computational elements to be arranged in pipelines.

RaPiD pipeline

Reconfigurable ASICs Problems with ASICs: Mask cost. Manufacturing time. Solution---mix ASIC and FPGA: Reconfigurable logic on bottom. Custom wiring on top.