EECS 473 Advanced Embedded Systems Lecture 9: Groups introduce their projects Power integrity issues

Project groups Please give a 2-3 minute overview of your project. Today: ARM chairs The group formerly known as ARM chairs, Glove, Waiter, Sign detect, ERP. Everyone else on Tuesday After this we’ll have ~90 second talks by half the groups each day. Keeping the same grouping Don’t worry about these They aren’t graded, they aren’t formal, they are merely informative. Just Spend 5 minutes thinking about what you want to say (and who will say it). Write down 3-5 talking points you want to touch so you can be sure you hit what you wanted to hit. Feel free to chime in if your speaker leaves something important out you want to say. Do ask questions. Turns out a “hummm… why are you doing X instead of Y?” or “Have you looked at part Z?” questions can really help (either your team or their team!). I’ll often provide some guidance for a given “week” of reports. This time is “give us an elevator pitch” Next time will be “What’s your status on part ordering, board design, and programming”

Final proposal due today Today Thursday @11pm I should have signed group agreement now. I should have feedback by Monday night to all groups.

Where we are; where we are going Labs 1-3 done, lab 4 due this week PCB lab Much less conceptual—it’s about learning a tool Entering full-time project mode. Have midterm and 2 homework assignments before project due. Everything else is project (and lecture). HW1 posted by the end of the day. Due 10/18 (12 days from now) I expect it will take ~4 hours It’s a nice prep for the midterm. Also practice midterms are posted. You should be putting in ~15 hours/week into the project. The more you put in now, the less you have later. And some things (reorders, PCB redos) just take time—can’t cram. You really (really) want time to debug! Large part of project grade based upon fully working. More complex projects get a bit more slack, but… Project due a week before classes end (design expo)

Power Distribution Network Power Integrity Power Distribution Network Talked a lot about keeping the power supply voltage constant. Should think of situation as follows: If the processor drops 3.3V and uses 100mA, what is it’s effective resistance? If the power supply is 3.3V, the processor uses 100mA and the total resistance of the PDN (Power distribution network) is .01Ω, what voltage does the processor really see? Input PDN Processor Output

Consider an FPGA with the following characteristics Acceptable voltage range is from 2.65 to 2.75V Max current is 5A. What is the largest impedance we can see on the PDN and still have this work?

Given the previous table.. Power Integrity Given the previous table..

Power Integrity Removing the PCB…

Power Integrity But wait… VRM Voltage regulator module bulk bypass (tantalum) and decoupling capacitors (ceramic). These capacitors supply instantaneous current (at different frequencies) to the drivers until the VRM can respond.  However sets of different capacitors cause problems! http://www.pcbdesign007.com/pages/columns.cgi? artcatid=0&clmid=65&artid=85396&pg=3&_pf_=1

Other power integrity issues Of course, one source of power integrity problems is coming from the processor Power supply just can’t keep up with processor varying (what we just did) But there are other problems. And these are issues introduced by the PCB designer. Don’t be that guy/gal.

Connecting ground poorly Power Integrity Connecting ground poorly One big issue is that people think of ground as, well, ground. It isn’t. Only one point is “0V”. Everything else has a higher voltage. Wires aren’t perfect. It’s really easy to make this mistake. Classes like EECS 215 basically encourage it. Better to think of things as “return path” not ground. And yes, you can make the same mistake with power, but people do that a lot less often. Partly because we often have different “Vcc” levels on the board. But mostly because we just think of power and ground differently.

Consider the following Power Integrity Consider the following Consider the figure on the right. Why is the top picture “wrong”? Let’s consider the case of “A” being DC motor that runs at 120 Watts (12V 10A). B is processor drawing 100mA Wire from A to PSU return is 15cm long, 400mils wide. What is the voltage at the “ground”? 0.1A 0.02Ω 10A 3.3V 12V Top figure from “The Circuit Designer’s Companion”. If you are going to do PCB design much, buy and read this book.

Review: Power integrity (1/2) Processors and other ICs have varying current demands Sometimes at frequencies much greater than the device itself runs at Why? So the power/ground inputs need to be able to deal with that. Basically we want those wires to be ideal and just supply how ever much or little current we need. If the current can’t be supplied correctly, we’ll get voltage droops. How much power noise can we accept? Depends on the part (read the spec). If it can run from 3.5V to 5.5V we just need to insure it stays in that range. So we need to make sure that given the current, we don’t end up out of the voltage range. Basically need to insure that we don’t drop too much voltage over the wires that are supplying the power!

Review: Power integrity (2/2) So we need the impedance of the wires to be low. Because the ICs operate at a wide variety of frequencies, we need to consider all of them. The wires themselves have a lot of inductance, so a lot of impedance at high frequencies. Need to counter this by adding capacitors. Problem is that the caps have parasitic inductance and resistance. So they don’t help as well as you’d like But more in parallel is good. Each cap will help with different frequency ranges. We also can get a small but low-parasitic cap out of the power/ground plane. Finally we should consider anti-resonance*. * http://www.n4iqt.com/BillRiley/multi/esr-and-bypass-caps.pdf provides a very nice overview of the topic and how to address it.

Power Integrity (PI) summary Power integrity is about keeping the Vcc/ground difference constant and at the value you want. Covered two issues: Many devices that sink power do so in “pulses” Due to internal clocks and time-varying behavior Need caps to keep value constant But parasitic ESR/ESL cause problems So lots of them==good Reduce ESR/ESL Increase capacitance. Anti-resonance can cause problems! Need Spice or other tools to model. Will do a bit of this next time Also, need to watch return paths Can easily bump up your ground level Cuts into your margin for the work above…

Additional “reading” http://www.murata.com/en-us/products/emiconfun/capacitor/2013/02/14/en-20130214-p1 Very nice coverage of ESR and impedance in a non-idea capacitor. Touches on the fact that ESR varies by frequency! Very readable and short! http://ksim.kemet.com/ Nice spice models of real capacitors. http://doc.utwente.nl/64874/1/tiggelman.pdf A much more academic treatment of ESR. https://www.youtube.com/watch?v=sW0a9d_vWoc Mildly amusing and useful (who doesn’t like magic smoke?)