3D Integrated Circuits: Their Fabrication and Devices Fabricating 3D integrated circuits and an overview of the fundamental techniques used. Samuel Jacobs EE4611 4/5/2017

Overview 2D vs. 3D integrated circuits Approaches to manufacturing 3D ICs Through Silicon Vias (TSVs) Wafer to Wafer Bonding Market Forecast for 3D ICs www.britannica.com

Market Projections: 3D over 2D Integration https://www.slideshare.net/NareshChinnu1 Reduced areal footprint by stacking layers up. Reduced interconnect distances. Reduced delay times Reduced power dissipation Mixed-Signal integration becomes more trivial. Greater technology lifetime of expensive photolithography techniques and machines. ice.ece.drexel.edu

3D over 2D Integration Design of 3D Integrated Circuits and Systems Rohit Sharma electronicdesign.com

Fabricating the 3D IC: Additive Approach www.ll.mit.edu Fabricate devices on first Si layer Mask Dope Oxide Growth Etch Deposit Interconnect metals Grow next Si layer Repeat from Step I Critical roadblocks with Si Grain Size Control Interconnect phase transition Diffusion of dopants There’s a better approach (today) Aluminum / Copper Phase Diagram www.imetllc.com/phase-diagrams/ www.researchgate.net

Fabricating the 3D IC: Top Down Approach Design of 3D Integrated Circuits and Systems Rohit Sharma Fabricate Semiconductor wafers independently. Wafers thinned from the backside Through Silicon Via Fabrication Align & bond individual layers together. Encapsulate completed IC

Through Silicon Vias (TSVs) Vias may be produced at several different process steps: Within Layer Fabrication After layer bonding TSV process: Mask & Etch Via Electrical Isolation Metal Deposition Diameter of Vias typically in micron range Reduced Interconnect delay times Reduced alignment error risk during bonding steps. Three-Dimensional Integrated Circuit (3D IC) … www.ll.mit.edu

Etching TSVs Wet Etch Dry (Plasma) Etch Bosch Process – Nearly Perfect Anisotropy Wet Etch Highly Isotropic All but infeasible Dry (Plasma) Etch Chemical Plasma Etching Rapid, but Isotropic. Reactive Ion Etching “Bosch Process” Highly anisotropic for P < 100 mTorr Once etched, Vias are insulated and conductively filled. wcam.engr.wisc.edu Design of 3D Integrated Circuits and Systems Rohit Sharma www.mems-exchange.org www.normandale.edu

Isolation and Metal Deposition of TSVs Etched Via must be insulated Dielectric deposition E-field reduced by dielectric Reduce parasitic capacitance Electrically isolates via from bulk Si Once isolated, Via is filled with conductive metal First, deposit thin seedlayer with sputter Promotes adhesion of bulk deposited metal. Via is then electroplated Must be void free Must match metal thermal expansivity (CTE) to that of bulk material http://www.oxfordplasma.de www.researchgate.net

Layer to Layer Bonding Two highly planar layers aligned to each other Layers then bonded together. Several techniques for bonding: SiO2: Two SiO2 surfaces brought together and annealed at high T Adhesive: 2 Polymer layers brought together and cured. Metal-Adhesive: Metal from one layer brought into contact with polymer from other layer. Metallic Bonding: Use of solder to attach layers Design of 3D Integrated Circuits and Systems Rohit Sharma

Fabrication Recap Separate Semiconductor layers produced in parallel Some may contain vias which are aligned & Bonded later Each layer thinned when fabrication is complete Vias may be fabricated on layer prior to thinning Through Silicon Vias fabricated Can be on their own separate blank Si layer, or integrated within previously fabricated layers. Separate layers aligned then bonded together. Several methods to bond. Additional Via production may occur after Encapsulation of material

Forecast & Devices 2013 – Samsung 3D Flash (Pictured Right) 2018 – 3D DRAM by Nvidia for their GPU Within 10 years – 3D CPU Benefit of partitioning functional blocks in 3 dimensions instead of 2. Will emerge as miniaturization continues to hit roadblocks. ie).Time delays are already at near unacceptable rates for feature size < 22 nm.

Summary 3D integrated circuits are a promising next step for Semiconductors. Reduced delay times and power dissipation over 2D Top down fabrication more efficient than additive “bottom up” approach TSVs and wafer bonding cornerstone technology for 3D ICs Market selection of 3D ICs is currently limited to DRAM only 3D ICs will expand into processors as technology roadmaps are constrained by 2D

References Sharma, Rohit, Krzysztof Iniewski, and Sung Kyu Lim. Design of 3D Integrated Circuits and Systems. Boca Raton, Fla.: Taylor & Francis/CRC, 2015. Web. Salah, Khaled, Yehea Ismail, and Alaa El-Rouby. "3D/TSV-Enabling Technologies." Analog Circuits and Signal Processing Arbitrary Modeling of TSVs for 3D Integrated Circuits (2014): 17-47. Web. Shen, Wen-Wei, and Kuan-Neng Chen. "Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)." Nanoscale Research Letters 12.1 (2017) "Quantum Information and Integrated Nanosystems." MIT Lincoln Laboratory: Advanced Technology: Quantum Information and Integrated Nanosystems. N.p., n.d. Web. 04 Apr. 2017. Rack, Phillip D. "Plasma Etching Outline." University of Tennessee, Knoxville. 3 Apr. 2017. Lecture. "The Coming Age of 3D Integrated Circuits." Hackaday. N.p., 08 Feb. 2016. Web. 04 Apr. 2017.

5 Key Concepts Power losses increase with reduced gate length Delay times increase with reduced interconnect area and increased interconnect length 3D Integrated Circuits can be manufactured by fabricating wafers in parallel and then bonding them together. Reactive Ion Etching with the Bosch process can produce almost perfectly anisotropic silicon wells Separate wafers may be bound together by annealing SiO2 together, with polymer adhesive, or by a combination of polymer adhesive on metal.