FPGAs for next gen DAQ and Computing systems at CERN 14/09/2016 ICE-DIP Final workshop Srikanth Sridharan

Srikanth Sridharan – ICE-DIP Project 14/09/2016

The Challenge Upgrades planned for LHCb exp. at CERN 40M particle collisions per sec Or a new collision every 25ns Data @40Tb/s Capture 100% of the data Currently capturing only 2.5% Trigger decisions (current) <4us for L0 <10ms for HLT * Projections from High Throughput Computing Project Status Report 22/6/16 by Niko Neufeld Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project The implication Need large computing infrastructure Impossible with just CPUs - need accelerators FPGA attractive due to performance and power efficiency Srikanth Sridharan – ICE-DIP Project 14/09/2016

High Throughput DAQ - Header Generator 1/2 The bitlines of each channel grouped in bytes Back Pressure / Stop signal Streaming data Non stop input Stop & Go output Event size info in 1.5 byte (12 bits) To packetize Create meta header Real time Time / Clock Srikanth Sridharan – ICE-DIP Project 14/09/2016

High Throughput DAQ - Header Generator 2/2 The bitlines of each channel grouped in bytes Back Pressure / Stop signal Discard events selectively Data rate down to 6-7% of normal Throughput >50GBps Current system 4GBps No other technology But FPGA Time / Clock Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project FPGA pains Programmability, Programmability, Programmability Hardware Description Languages (VHDL, Verilog) Register transfer level (RTL) abstraction Manage Memory access, Communication Create PC side SW, drivers Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project OpenCL for FPGA 1/2 An unified programming model for application accelerating on heterogeneous systems C based programming language System level design (Host CPU+FPGA) Memory Hierarchy auto generated Host CPU-FPGA communication abstracted away Potential to integrate existing VHDL/Verilog IP Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project OpenCL for FPGA 1/2 Srikanth Sridharan – ICE-DIP Project 14/09/2016

OpenCL Algorithm Acceleration 1 Hough Transform For particle track reconstruction LHCb VertexDetector Find tracks from the Hit data of the detector Exisiting OpenCL GPU code ported to FPGA Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project Hough transform cont. Srikanth Sridharan – ICE-DIP Project 14/09/2016

OpenCL algorithm acceleration 2 RICH Cherenkov angle reconstruction Reference: Intel Core i7-4770 Srikanth Sridharan – ICE-DIP Project 14/09/2016

Cherenkov angle reconstruction cont. FPGA has 1.4X better overall performance over GPU (normalized) FPGA has 3.4X and 6.6X Performance/Watt Vs GPU and CPU Srikanth Sridharan – ICE-DIP Project 14/09/2016

OpenCL for more than acceleration? How about a DAQ system with OpenCL? Attempted implementation of Header Generator in OpenCL Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project CPU – FPGA integration Data transfer time > Compute time Low latency, coherent memory access technologies IBM CAPI and Intel QPI Preliminary results very exciting Significant overall runtime reduction Srikanth Sridharan – ICE-DIP Project 14/09/2016

Accelerating Productivity OpenCL – a game changer for FPGAs Accelerated development ~2 weeks for OpenCL vs ~2 months for RTL System level design Combined development for host and FPGA Code portability Move between CPU, GPU, FPGA, Xeon Phi Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project Everybody FPGAs Intel – Buys Altera Add FPGA to every CPU Microsoft – Project Catapult: Bing Looking to add FPGAs to every server node IBM – various efforts: cognitive computing, IOT “….no better technology halfway between CPUs and ASICs…” Baidu, Google, Huawei, BMW, Uber… CERN – ??? Hint: I can help  Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project Future work Extend OpenCL for FPGA Further investigate CPU-FPGA integration Explore other programming models for CPU-FPGA systems Explore other application domains Genomic, Financial, Weather/flow/seismic modeling, Radio astronomy, Sensor Fusion, IOT… Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project Papers Dynamically Adaptive Header Generator and Front-End Source Emulator for a 100 Gbps FPGA based DAQ - RT2014 Evaluation of ‘OpenCL for FPGA’ for Data Acquisition and Acceleration in High Energy Physics - CHEP2015 and Journal of Physics: Conference series LHCB Technical Note: Evaluation of ‘OpenCL for FPGA’ for Acceleration and DAQ in HEP Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures - FPL2016 Srikanth Sridharan – ICE-DIP Project 14/09/2016

Srikanth Sridharan – ICE-DIP Project 14/09/2016