ETD meeting Architecture and costing On behalf of PID group Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting Introduction A robust and simple TDC based solution (BABAR-like) is the baseline for the PID barrel even if there are still ongoing discussions on analog memories. They are the baseline for the TOF electronics (few channels. Ultra fast PMs) The white paper describes a global architecture for the Barrel and the associated costing. A few key numbers : High number of channels => 36k / 18k High trigger rate => 150 kHz No T0 for trigger matching => ~ 200 ns window Background: 1MHz worst case . Little physical space and some radiation level on the detector => Limitation of electronics in terms of quantity and « intelligence » on detector Limitation of power Design with mitigation methods Design with technology compatible with low level radiation as expected on the DIRC Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting Former calculation of the event size is based on the simplest (BABAR-like) option: We encode the hit arrival with a 100-ps TDC If we feel like adding the charge information for each hit, data word may rise up to 48 bits => factor 1.5 on number of links. From what has just been shown, it becomes obvious that our system will be topology driven concerning the number of links with the TDC based solution. This was already the case in BABAR’s DIRC: 12 readout links each with a payload of 15 to 20% of its capacity. Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting One link per sector looks appealing. This very small number of links gives a pleasant (and anyhow necessary) safety factor for all potential increases in the background rate (H), trigger rate (T) or window width (W). Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting Electronics is split in two parts : one directly mounted on the PM base receiving the PM signal and processing it with TDC/ADC the other one concentrating and packing all the channels to send data to the DAQ Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting Global architecture Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting Ongoing work Design of a new TDC based on the existing one Redesign of the readout and a few improvements on the Front end part Programmable number of bits for the time counter. New derandomizing FIFOs : depth of 32 events ( each of 4 * 16-bit data word) Data push at the output Run end 2010. AMS .35 um technology. Chip first quarter of 2011. We now have to work on the way to interface the chip with the acquisition design proposed in Proposal for the Electronics Trigger and DAQ architecture Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting We have a board in hand with the first version of the SNATS and a FE chip. It could be used for a first test on the CRT @ SLAC. This depends on our manpower and on the availability of SLAC colleagues to interface it to the local DAQ. The New version of the SNATS will be available first quarter of 2011 Do we develop a board for this new chip to test it on the CRT ? A first prototype of the FE ASIC will be available end 2011. We can produce a first DIRC FE prototype mid 2012. Mars 16th 2010 Christophe Beigbeder ETD Meeting

Christophe Beigbeder ETD Meeting Costing PID BARREL Front-end electronics FE-IC-1 prototypes + prod (qty 10 + 100 + 4000) FE-IC-2 prototypes + prod (qty 10 + 100 + 4000) FE boards (including FPGA) (qty 5 + 20 + 500) Cables between FE and concentrator (qty 500) Concentrator electronics Concentrator boards (qty 50) Concentrator control boards (qty 6) Concentrator crates (qty 6) Concentrator backplanes (qty 6) Concentrator prototyping LV supplies LV Power Supplies LV cables HV supplies HV Power Supplies HV cables Final installation Electronics test Bench 510 275 100 125 25 55 15 6 18 10 44 36 8 48 12 3 Mars 16th 2010 Christophe Beigbeder ETD Meeting