Triplets Baseband Overview Edwin Gonzalez

Regulators Vbuck, 1.875V +/- 4% Sources Neptune Core Vboost 5.6V +/- 5% Source for V10 & keypad backlights V1 = I/O REG, 2.875V +/- 3%, Neptune I/O Reg 2.875 +2/-4% Sources Neptune I/O, ATI Graphics Accel I/O Ring, Camera, SPI interfaces V3 = VA1.2, Starts at 1.575V then SW selected to 1.275 +/-3% Sources ATI Graphics Accel core V4/V5 = tied to V1, programmed to OFF, but source internal PCAP circuitry V6 = NC V7 = RF_REG, 2.875V +/- 3% Sources Algae and Support circuitry. V8 = BTRF, 1.875V +/- 3% Sources Blue Tooth circuitry V9 = REF_REG, 1.575 V +/- 3% RTC and Neptune reference V10 = RF_5V_REG, 5V +/- 3%

PCAP Regulators Sequencing

Charger Works exactly the same as the P2k products All the FETS are PFETs Charger FET runs linearly with all chargers, PCAP controls Gate voltage based on Voltage Sense across Sense Resister Midrate FET– Allows for connection of the charger to the phone Main FET– controls whether battery is connected to the phone, OVIC– Threshold is 6.9+/- 0.2V Fast Rate Charger, OVIC is ON Charger is in Linear mode passing ~500mA Midrate FET is ON Main FET is OFF When phone is active it pulls all the current from the charger, and left over will continue to charge the battery.

Charger –Cont’d Midrate Charger , while phone is in standby or Charge only mode OVIC is ON Charger is in linear mode, the amount of current passing from charger to battery is dependent upon battery voltage Main FET is OFF Midrate Charger, While in a call or using camera/pda/or other high current tasks Midrate is OFF Charger is in linear mode Main FET is ON This particular mode of the charger is not fully implemented in the SW and the HW engineers are currently working through the details of what the phone should do under different load conditions. Follow up material will need to be completed once these details have been worked out.

Charger

Charger

RX Audio

TX Audio

PCAP

Neptune LTE (U800) RF connection is same as with LCA architecture PCAP interface is very similar to P2K, uses a SPI to read and write registers, & variety of port lines to pass data. Display and Camera are interfaced through the ATI Graphic Accelerator. Data is passed to the Graphic Accel through the DMAC of Neptune. Data is passed back to Neptune through the SPI. All direct control of the camera and display is handled by ATI part. Funlights/LCD Backlights driver is controlled via SPI, same SPI for PCAP & ATI part. Bluetooth connections is through a UART. Keypad, is same implementation as on P2K products CE Bus should behave same as it does for P2K

Neptune LTE (U800)

26 MHz Clock, Y805 This clock is required for Neptune to come up fully and run at full speed. Without the presence of this clock the phone will start to power up and immediately shut down. No communication with Neptune will be available This clock is also used by TXVR and must be very clean.

Flash/SRAM Memory, U700 Triple stack part Two Tyax 128Mbyte Flash One PseudoSRAM 32Mbyte IMEI is stored in the FLASH Replacing Neptune or Memory Device Neptune and Memory are under a shield and possible to replace, but difficult. If Field service chose to replace FLASH, IMEI would need to be reprogrammed. Neptune is a 280 pin bga, difficult to replace, but possible. There are new Security enhancements that are not fully implemented yet.

Flash/SRAM Memory, U700

Bluetooth System Block SAP BLUE HOST WAKE Neptune LTS/LTE PCAP BLUE WAKE 26MHz XTAL UART2 95L14 Bluetooth Module BTRF_REG = 1.8VDC 26MHz XTAL IO_REG = 2.775VDC

Bluetooth

Flip LCD Modules This display is a color Active Matrix Liquid Crystal Display (AMLCD) module of glass construction with black pixels on a white background. The display consists of 176 (x RGB Stripe) x 220 pixels with 64K colors. There are a few different displays from different vendors Samsung TF, Samsung TMR and Sharp TF The Samsung TF and Sharp TF will be used on V300 & V600 (Only on V300 the situational lighting tail will be cutoff) The Samsung TMR is a 98% transmissive display that w/o the LCD backlight the display is completely black.

Flip Block Diagram

Camera On camera: from hardware perspective, if they can open the flip and probe the 20-pin zif connector on the display module, while the camera is connected verify following: First place the camera in view finder mode either through UI or using test command and check following signals: · B+ = 2.775 Vdc on pin 2. · Check input clock from ATI chip on pin 19, Clock freq ~ 13 - 14 MHz · Check output clock to ATI on pin 18. Should be same as input clock · Check control signals logic level. Both PD (pin 12) and RS (pin 13) should be logic low below ~).7 Vdc · Check on oscilloscope that D0 - D7, data lines (pin 4 - 11), are randomly toggling during viewfinder · Check periodic synch signals, HS (pin 16) and VS (pin 15) on oscilloscope. They should have periodic format during viewfinder. · Check I2C lines SDA (pin 14) and SCL (pin 17). When a test command or any command sent to the camera it goes over this 2-pin bus and make sure that lines are toggling upon command sent. If any of the above is too complicated and time consuming then take the camera out place new camera and see it works. If that does not work then replace the display module. If that does not work, then get a new phone!