Outline Analog to digital conversion (ADC) of NuMaker TRIO

Slides:



Advertisements
Similar presentations
I2C bus Inter Integrated Circuits bus by Philips Semiconductors
Advertisements

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Guest Lecturer Pat Pannuto Lecture 10: Serial buses Oct 6, 2011.
Embedded Systems I2CI2C. Feature 3 wire GND SCL(clock) SDA(data) All devices share the same bus wire Using wire and, each device gain access to bus (become.
Serial Interfaces, Part Deux -I 2 C and SPI December 4, 2002 Presented by Eugene Ho.
Lecture 8: Serial Interfaces
SPI on the ATmega SS’ line only used in Slave mode SPDR
9/20/6Lecture 3 - Instruction Set - Al Hardware interface (part 2)
I2CI2C CS-423 Dick Steflik. Inter-Integrated Circuit Developed and patented by Philips for connecting low speed peripherals to a motherboard, embedded.
Lecture 27: LM3S9B96 Microcontroller – Inter- Integrated Circuit (I 2 C) Interface.
Haptic Belt team Informational Presentation.  I 2 C is a form of control bus (multi-master) which allows communication between multiple integrated circuits.
1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 10: Serial buses Oct 6, 2011.
1 © Unitec New Zealand I2C Lecture 10 Date: - 2 Nov, 2011 Embedded Hardware ETEC 6416.
Introduction Electrical Considerations Data Transfer Synchronization Bus Arbitration VME Bus Local Buses PCI Bus PCI Bus Variants Serial Buses 11/06/20141Input/Output.
Lecture 111 Lecture 11: Lab 3 Overview, the ADV7183B Video Decoder and the I 2 C Bus ECE 412: Microcomputer Laboratory.
LSU 10/22/2004Serial I/O1 Programming Unit, Lecture 5.
VERIFICATION OF I2C INTERFACE USING SPECMAN ELITE By H. Mugil Vannan Experts Mr. Rahul Hakhoo, Section Manager, CMG-MCD Mr. Umesh Srivastva, Project Leader.
Embedded Bus – i2c David E. Culler Lab 2 Feb 2, 2015
4.0 rtos implementation part II
7/23 Inter-chip Serial Communication: SPI and I 2 C Computer Science & Engineering Department Arizona State University Tempe, AZ Dr. Yann-Hang Lee.
Lecture 20: Communications Lecturers: Professor John Devlin Mr Robert Ross.
DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK
Atmel Atmega128 Overview ALU Particulars RISC Architecture 133, Mostly single cycle instructions 2 Address instructions (opcode, Rs, Rd, offset) 32x8 Register.
1 Synchronous Serial IO Send a separate clock line with data –SPI (serial peripheral interface) protocol –I 2 C (or I2C) protocol Encode a clock with data.
Refer to Chapter 15 in the reference book
©2008 R. Gupta, UCSD COSMOS Summer 2008 Peripheral Interfaces Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
© 2009, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose:  This course provides an overview of the serial communication.
Essentials of Communication This simple model requires many guarantees. Sender Receiver Communication Link Data.
Serial Peripheral Interface SPI I2C (i-squared cee)
© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose  This course provides an introduction to the peripheral functions.
میکرو کنترلرهای AVR Serial Interfaces, I2C and SPI
MICROCONTROLLER AND INTERFACING Presented by: Shefali Jethva ( ) Shivali Panchal ( ) Komal Soni ( ) Roll no. :- 14EC308.
Lab 9 Multiprocessor, Buses, SPI, I2C. Multiprocessors Why multiprocessors? The structure of multiprocessors. Elements of multiprocessors: – Processing.
USING TV REMOTE AS A CORDLESS MOUSE FOR THE COMPUTER
CORDLESS MOUSE FEATURES BY TV REMOTE USING PIC MICROCONTROLLER
Recall Our TWR-K60D100M Primary SW1 Connector SW2 SW3(Reset) Secondary
Outline Introduction to NuMaker TRIO Programming environment setup
Outline Introduction to digital-to-analog converter (DAC)
Department of Computer Science and Engineering
Serial Communication Originally created by Anurag Dwidedi and Rudra Pratap Suman.
Lecture 3 Cache Bus.
Microcontrollers, Basics Fundamentals of Designing with Microcontrollers 16 January 2012 Jonathan A. Titus.
Serial Communication Buses: I2C and SPI
Cortex-M0 MCU Clocks & Pins
The I2C Bus.
Two Wire Interface Another popular serial peripheral interface bus
Analog-to-Digital Converter (ADC)
EE 107 Fall 2017 Lecture 5 Serial Buses – UART & SPI
Inter-IC Bus (I C) 2.
Chapter 11: Inter-Integrated Circuit (I2C) Interface
I/O Memory Interface Topics:
CS4101 Introduction to Embedded Systems Lab 9: NuMaker ADC and LCD
(Inter-IC bus) By Tejaswini Gadicherla
1 Input-Output Organization Computer Organization Computer Architectures Lab Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes.
EE 107 Fall 2017 Lecture 7 Serial Buses – I2C Direct Memory Access
E3165 DIGITAL ELECTRONIC SYSTEM
I2C PROTOCOL SPECIFICATION
Communication Lines Fundamentals.
BJ Furman ME 106 Fundamentals of Mechatronics 15NOV2012
EEPROM Comparison – Parallel or Serial
Introduction to Microprocessors and Microcontrollers
Interfacing Memory Interfacing.
Chapter 7 Features and Interfacing of Programmable Devices for 8085 based systems.
Serial EEPROM (Atmel 24C-512)
I2C and RTC Chapter 18 Sepehr Naimi
Преглед Начин функционисања Имплементације
X1 & X2 These are also called Crystal Input Pins.
AVR – ATmega103(ATMEL) Architecture & Summary
8253 – PROGRAMMABLE INTERVAL TIMER (PIT). What is a Timer? Timer is a specialized type of device that is used to measure timing intervals. Timers can.
Prof. Chung-Ta King Department of Computer Science
Serial Communication 19th Han Seung Uk.
Presentation transcript:

CS4101 嵌入式系統概論 NuMaker TRIO: ADC, I2C, LCD Prof. Chung-Ta King Department of Computer Science National Tsing Hua University, Taiwan

Outline Analog to digital conversion (ADC) of NuMaker TRIO I2C and LCD of NuMaker TRIO

ADC of NuMaker TRIO 12-bit successive approximation 8 external input channels and 4 internal channels ADC can be started by software, external STADC (PA.11) pin, timer event and PWM trigger SAR DAC Comparator Clock Vref End-Of-Conversion Vin Sample & Hold - + N-bit

ADC Block Diagram

Three Operation Modes Single mode: Single-cycle scan mode: A/D conversion is performed one time on a specified channel Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel Continuous scan mode: A/D converter continuously performs single-cycle scan mode until software stops it

smpl_ADC4_GL5516 (SampleCode/NuMaker-TRIO) // Define Clock source #define MCU_CLOCK_SOURCE #define MCU_CLOCK_SOURCE_HIRC // HXT, LXT, HIRC, LIRC #define MCU_CLOCK_SOURCE_LXT #define MCU_CLOCK_FREQUENCY 32000000 //Hz // Define MCU Interfaces #define MCU_INTERFACE_ADC #define ADC_CLOCK_SOURCE_HIRC // HXT,LXT,PLL,HIRC,HCLK #define ADC_CLOCK_DIVIDER 1 #define PIN_ADC_4 // To Photoresistor or IR Diode #define ADC_INPUT_MODE ADC_INPUT_MODE_SINGLE_END // SINGLE_END, DIFFERENTIAL #define ADC_OPERATION_MODE ADC_OPERATION_MODE_CONTINUOUS // SINGLE, SINGLE_CYCLE, CONTINUOUS A differential ADC will measure the voltage difference between two pins (the plus and minus input). A single-ended ("regular") ADC will measure the voltage difference between one pin and ground.

smpl_ADC4_GL5516 (SampleCode/NuMaker-TRIO) void Init_ADC(void) // Initialize ADC { ADC_Open(ADC, ADC_INPUT_MODE, ADC_OPERATION_MODE, ADC_CHANNEL_MASK); ADC_POWER_ON(ADC); // Enable ADC interrupt ADC_EnableInt(ADC, ADC_ADF_INT); NVIC_EnableIRQ(ADC_IRQn); //ADC conversion start ADC_START_CONV(ADC); }

SYS_init.h (Library/NuMakerLib/Include) #ifdef PIN_ADC_4 #define ADC_CHANNEL_MASK_4 ADC_CH_4_MASK #else #define ADC_CHANNEL_MASK_4 0 #endif ... #define ADC_CHANNEL_MASK (ADC_CHANNEL_MASK_0 | ADC_CHANNEL_MASK_1 | ADC_CHANNEL_MASK_2 | ADC_CHANNEL_MASK_3 | ADC_CHANNEL_MASK_4 | ADC_CHANNEL_MASK_5 | ADC_CHANNEL_MASK_6 | ADC_CHANNEL_MASK_7)

Outline Analog to digital conversion (ADC) of NuMaker TRIO I2C and LCD of NuMaker TRIO On NuMaker TRIO, CPU communicates with LCD display via the I2C bus

I2C Serial Communication I2C: Inter Integrated Circuit Bus Two-wire serial multimaster-slave bus protocol by Philips in the 1980s Enables peripheral ICs to communicate using simple communication hardware 7-bit or 10-bit address space Data transfer rate: 100 kbits/s (standard mode), 400 kbits/s (fast mode), 3.4M bits/s (high speed mode) Common devices capable of interfacing to I2C bus: EPROMS, Flash, and some RAM memory, real-time clocks, watchdog timers, and microcontrollers

I2C (Inter Integrated Circuit) I2C is a two-wire, bi-directional synchronous serial bus supporting multiple masters with collision detection and arbitration Serial 8-bit bi-directional data transfers up to 1 Mbps between a Master and a Slave according to SCL on the SDA line Vdd SDA (Serial Data Line) SCL (Serial Clock Line) SCLKN1 out SCLK in DATA1 out DATA in

I2C Bus Structure 2 signal lines: SCL (serial clock), SDA (serial data) Every device connected to the I2C bus has a unique address and can act as a receiver or a transmitter I2C is a multi master bus. Bus master is established at the time of communication

I2C Protocol Transfers are byte oriented, MSB first Quiescent state for SCL, SDA is HIGH Start: Master sends SDA low while keeps SCL high Master sends address of slave (7-bits) on next 7 clocks Master sends read/write request bit 0 (write to slave), 1 (read from slave) Slave ACKs by pulling SDA low on next clock

I2C Protocol Master transfers one-byte of data to slave on next 8 clock pulses Clock is controlled by master Data receipt is ACKed by slave on 9th pulse by pulling SDA low When slave releases, SDA master can send next byte At the end of transmission, Master sets a Stop condition by making a low to high transition on SDA with SCL is high

Timing Diagram of I2C Protocol Data transfer initiated with a START bit (S) signaled by SDA being pulled low while SCL stays high. SDA sets 1st data bit level, keeping SCL low (blue) Data is sampled (received) when SCL rises (green) This process repeats: SDA transitioning while SCL is low, and data being read while SCL is high A STOP bit (P) is signaled when SDA is pulled high while SCL is high (wikipedia)

I2C Transaction Transmitter/receiver differs from master/slave Master initiates transactions Slave responds Transmitter sets data on SDA line, slave acks For a read, slave is transmitter and master acks For a write, master is transmitter, and slave acks

Arbitration Two transmitters may start transmission at about the same time  need arbitration If one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter observes that the level of the line is different from that expected. It concludes that another node is transmitting and it loses arbitration In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA, and therefore continues transmission

I2C Protocol Four parts in a standard communication: START or Repeated START signal generation Slave address transfer Data transfer STOP signal generation When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer.

I2C Protocol: Start and Stop Bus is free/idle when both SCL and SDA are high A master initiates a transfer by sending START signal A HIGH to LOW transition on SDA while SCL is HIGH A STOP signal to terminate the communication a LOW to HIGH transition on SDA while SCL is HIGH When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer.

I2C Protocol: Bit Transfer Each bit is sampled during the high period of SCL SDA may be changed only during the low period of SCL and must be held stable during the high period of SCL A transition on the SDA line while SCL is high is interpreted as a command (START or STOP)

I2C Protocol: Slave Address Transfer The 1st byte transferred by Master after START signal A 7-bits calling address followed by the R/W bit to indicate the data transfer direction The matching slave responds by returning an acknowledge bit by pulling SDA low at the 9th SCL clock cycle

I2C Protocol: Data Transfer Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle If the slave signals a NACK, the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle If the master, as the receiving device, send NACK to the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal

smpl_I2C_LCD (SampleCode/NuMaker-TRIO) MCU_init.h //Define Clock source #define MCU_CLOCK_SOURCE #define MCU_CLOCK_SOURCE_HIRC // HXT, LXT, HIRC, LIRC #define MCU_CLOCK_SOURCE_LXT #define MCU_CLOCK_FREQUENCY 32000000 //Hz //Define MCU Interfaces #define MCU_INTERFACE_I2C1 #define I2C1_CLOCK_FREQUENCY 400000 //Hz #define PIN_I2C1_SCL_PC10 #define PIN_I2C1_SDA_PC11

smpl_I2C_LCD (SampleCode/NuMaker-TRIO) main.c #include <stdio.h> #include "Nano1X2Series.h" #include "MCU_init.h" #include "SYS_init.h" #include "I2C_SSD1306Z.h“ int32_t main(){ SYS_Init(); I2C_Open(I2C1, I2C1_CLOCK_FREQUENCY); Init_LCD(); clear_LCD(); print_Line(0, "NuMaker TRIO"); print_Line(1, "Cortex-M0 @32MHz"); }

I2C_SSD1306.c (Library/NuMakerLIb/Source) void print_C(uint8_t Line, uint8_t Col, char ascii) { uint8_t j, i, tmp; for (j=0;j<2;j++) { lcdSetAddr(Col*8, Line*2+j); for (i=0;i<8;i++) { tmp=Font8x16[(ascii-0x20)*16+j*8+i]; lcdWriteData(tmp); } } } void print_Line(uint8_t line, char text[]) { uint8_t Col; for (Col=0; Col<strlen(text); Col++) print_C(line, Col, text[Col]); void lcdWriteData(uint8_t lcd_Data){ uint8_t data[1]; data[0]=lcd_Data; I2C_writeBytes(LCD_I2C_PORT,LCD_I2C_SLA,0x40,1,data);