LVDS Project: A RAD-HARD 500 Mbps LVDS Bus for Space June 12-16, 2016 AMICSA & DSP DAY 2016 1

Agenda Introduction to the LVDS project LVDS Octal Repeater Characterization/Radiation Results LVDS Octal Repeater Evaluation Status LVDS – AMICSA & DSP DAY 2016

Introduction to the project - General LVDS project is an ESA funded project for the development of a European LVDS family for Space Phase 1: Preliminary design of a LVDS Octal Repeater Phase 2: Detailed Design, Manufacturing and Characterization of the LVDS Octal Repeater Phase 3: ESCC Evaluation of the improved LVDS Octal Repeater LVDS – AMICSA & DSP DAY 2016

Introduction to the project – Suppliers SOFICS: ESD Designer of Protection Cells IHP: Wafer Manufacturer in SGB25RH Technology HCM: Assembly House ALTER: Testing House LVDS – AMICSA & DSP DAY 2016

Introduction to the project – Main Milestones Project started: April 2012 End of Phase 1: August 2013 End of Phase 2: October 2015 Phase 3 CDR: January 2016 Phase 3 Tape-out: February 2016 Phase 3 Assembly: July 2016 Phase 3 Evaluation Testing: Q3 2016 Project ends: Q1 2017 LVDS – AMICSA & DSP DAY 2016

Introduction to the project – Features Key features of the octal LVDS repeater: 3,3V single Power Supply Cold Sparing 500Mbps Fail safe mode Low Channel to Channel Skew Tri-state output control Extended receiver Common mode ESD 8kV Radiation Hardness 300kRad, SEL free and BER=1E-13Err/day/bit LVDS – AMICSA & DSP DAY 2016

LVDS Octal Repeater Results – Electrical Charact. Test Set-up at ALTER: LVDS – AMICSA & DSP DAY 2016

LVDS Octal Repeater Results – Electrical Charact. Fulfillment of Project requirements and generic requirements of ANSI/TIA/EIA-644 apart for following electrical parameters: Parameters Description Measured Value Spec. Limit VTH LVDS Input Voltage Threshold 135mV <100mV tP Propagation time 5,5ns <3,5ns VOD Differential Output Voltage 565mV @-55ºC only <453mV ICS ICSOUT ICSIN Cold Spare Leakage currents 30uA @25ºC 50uA @125ºC <20uA IOZ Output Tristate Current 15uA <10uA JRMS Jitter rms 20ps <15ps LVDS – AMICSA & DSP DAY 2016

LVDS Octal Repeater Results – SEE According to ESCC25100 Standard Heavy Ion Test at UCL HIF facility with 4 ions (4 LET Energies) No sensitivity to Latch-up up to 62.5MeV.cm2/mg No sensitivity to SEU/SET up to 20MeV.cm2/mg 15 bit errors after 1E12 transmitted bits at 62.5MeV.cm2/mg LVDS – AMICSA & DSP DAY 2016

LVDS Octal Repeater Results – TID According to ESCC22900 Standard Total Ionizing Dose (Co60 Source) at RADLAB facility at LDR of 220Rad/h => No sensitivity to Total Dose up to 300kRad (Highest Tested Dose) LVDS – AMICSA & DSP DAY 2016

LVDS Octal Repeater Results – ESD According to ESD JEDEC Standards (JS-001-2010, JESD22-A115-A and JESD22-C101-C) ESD Pulses at ALTER Installation with HBM, MM and CDM Models => No sensitivity to ESD up to: ±8KV with HBM ESD model ±250V with MM ESD model. ±500V with CDM ESD model Note that ESD TLP Test Performed on wafer at IHP demonstrated forehand the robustness of ESD cells developed by SOFICS (>7kV) . LVDS – AMICSA & DSP DAY 2016

LVDS Octal Repeater Evaluation – Status Design Modification to Improve Electrical parameters Selection of a Suitable CQFP48 Package for Space Complete Wafer Manufacturing Run and Assembly in course at HCM The Evaluation tests (Based on ESCC2269000) will consider: Thermal Step-Stress SEE Radiation TID Radiation Construction Analysis Package Test ESD Endurance Tests LVDS – AMICSA & DSP DAY 2016

dgonzalez@arquimea.com jlopez@arquimea.com arquimea_012 arquimea_026 LVDS – AMICSA & DSP DAY 2016