ALICE-FOCAL status and plans 1 ALICE-FOCAL status and plans Taku Gunji Hideki Hamagaki Center for Nuclear Study, University of Tokyo

Physics Motivation of ALICE-FOCAL 2 Main physics topics: Gluon saturation (pA) Fully exploit the opportunity at the LHC to access smaller-x region & large saturation scale by going to forward rapidity. RHIC forward rapidity (h=3)  LHC mid-rapidity. Importance to understand initial state effects systematically at the LHC (pA). Thermalization mechanism (saturation  glasma) (AA) Systematic measurements of hot and dense medium (AA) Elliptic flow/ridge/jet quenching (AA) Provide forward (h>3) coverage for identified particle measurements EM calorimeters for (prompt) g, p0, h, heavy quark(onia), jets Requires high granularity (lateral and longitudinal) Favored technology: W+Si calorimeter

Location of FOCAL in ALICE 3 Detector Location Stage 1 (z=3.5m, 2.5<h<4.5) in 2016 Stage 2 (downstream, 4.5<h<6) in 2020. Need to modify the beam pipes and support stuffs. Project Institution CNS Tokyo, Yonsei, Kolkata, Mumbai, Jammu, Utrecht/Amsterdam, Prague, Jyväskylä, Copenhagen, Bergen, Oak Ridge, Nantes, Jaipur

Design candidate of FOCAL 4 W+Si pad/strip readout Combination of Si pad/strip readout Pad for energy & strip for position measurement Strip will be located at 2-6X0 (preshower) Pad size: 5-10mm square, Strip : 0.5-1mm pitch Analog out & FADC sampling possible W+ Si pixel readout Si pixel is famous as used in tracking device. Idea is to extend the capability as Calorimeter readout. Pixel size: 20-100um square Challenging for electronics. Dynamic range Digital out, serial readout, readout time, powers, rad-hardness Hybrid (W+Si pad/pixel readout)

Detector Design-I W+Si (pad/strip) calorimeter similar to PHENIX-FOCAL 5 W+Si (pad/strip) calorimeter similar to PHENIX-FOCAL CNS, India, Czech, ORNL,CERN One tower configuration First segment Second segment Third segment Si Strip (X-Y) Tungsten Si pad CPV 9cm W thickness: 3.5 mm (1X0) wafer size: 9.3cmx9.3cmx0.525mm Si pad size: 1.1x1.1cm2 (64 ch/wafer) W+Si pad : 21 layers 3 longitudinal segments Summing up raw signal longitudinally in segments (CNS) Or individual layer readout (Czech) Size: 9x9 cm2 Thickness: 535mm Pad size: 1.1x1.1 cm2 Number of pads : 64 Single sided Si-Strip (2X0-6X0) 0.7mm pitch (128ch/wafer) Possibility to replace to fine pixel readout!

Readout Flow Composition Summing board or flexible cable 6 Assemble jig Composition Summing board or flexible cable ASIC cards [analog out or QTC digital out] ADC(12-14bit)/TDC(TMC)+FPGA board SRU (scalable readout unit) Scalable Readout Unit Fast analog/digital out for trigger? ASIC Summing board ADC/TDC/FPGA Optical out CNS Czech amp + ADC

Brief development status 7 Current status of activities from each institute CNS Si pad/Si strip production Tower design, Jig for assembling, backboard/summing board design Analog ASIC for pads, strips (with CMS) Simulations India Strip development Pattern recognition of pi0 identification by strip Czech Tower design consideration (individual layer readout) ORNL ASIC development Another type of tower and readout design CERN ADC/TDC + FPGA board, SRU (great interests from CNS)

Detector Performance (Simulation) 8 Detector simulation linearity <1% up to 200GeV Resolution: 22%/sqrt(E) + 1.6% Position resolution by the strips at 4, 5, and 6 layer. Resolution ~ 0.25mm with 0.7mm pitch PYTHIA p+p 14TeV (MB) E>30 GeV (only pads)

Jig for assembling First prototype jug for assembling the pad layers 9 First prototype jug for assembling the pad layers Dummy material + summing board + HIROSE FPC/FFC connector Will be developed with iterations. HIROSE FPC/FFC connector Dummy material (3.5mm thickness plate + flexible cables) Summing board

ASIC development Pads readout : 1mm pixel and 0.7mm Strip readout: 10 Pads readout : Dynamic range: 50fc – 200pC . Cross talk < 1%. S/N=10@MIP Relatively fast readout is needed for L0 trigger generation. R&D of the ASIC is being done by CNS+RIKEN/KEK and ORNL Dual charge sensitive preamplifier using capacitive division QTC (charge-to-time converter, no CMOS switches) Dual transimpedance preamplifier Source follower (voltage amplifier) 1mm pixel and 0.7mm Strip readout: Dynamic range: 4fc – 2pC. PACE-III for strips (CMS preshower counter, LHCf W+Si readout) Discussion to use PACE-III has been started with CMS. Plan to develop pixel readout ASIC by CNS/RIKEN/KEK

Dual CSP Collaborative work with RIKEN and KEK Chigh Clow 11 Collaborative work with RIKEN and KEK Leading studies by RIKEN and KEK Development for our purpose ASIC training course in 2010 & MoU between CNS(UT)-RIKEN-KEK Submitted two types of prototype ASIC CSA + PZ + dual integarator (2nd shaper) CSA + PZ + dual integrator + QTC Available in Feb. Clow Chigh SA(high) SA(low) 1.8pF Clow = Chigh/10 7 mm 0.5 mm pitch lead 200pF Clow 560pF Chigh 5.6nF 10pF CSA PZ ASIC High side Low side

linearity 12 Shaper output Linearity of shaper out 2.5usec Linearity of QTC QTC output

Next plans for the ASIC R&D 13 Faster readout and trigger capability for pads Revisit our charge sensitive preamplifier To enlarge bandwidth, phase margin, open (closed) loop gain Another type of preamplifier Voltage amplifier Source follower at the 1st stage. Reading out individual layer is preferable. ORNL is interested in this way. Current amplifier Design is underway. Another type of QTC Constant current feedback at the preamplifier (no CMOS switches) Increase # of channels, reduce powers, radiation tolerance, R&D of ASIC for strips/pixels

Voltage amplifier Quick simulation using LTSPICE 14 Chigh 200pF Clow 1.8pF Chigh 18pF CSA Voltage at input gate Output V (low side) Input current (5pC/100MIP) Linearity (high/low) Output V (high side) 500ns

Current preamplifier Quick simulation by LTSPICE Zin=10Ohm 15 Quick simulation by LTSPICE Zin=10Ohm No gain (R) optimization More realistic calculation Conductance, capacitance, resistance in the input line Input current (0.1pC-150pA) Output (high, 1kohm) (0.1pC-150pA) Fast signal processing! high low Output (low, 0.1kohm) (0.1pC-150pA) Fast signal processing! 100ns

Detector Design-II hexagonal towers proposed by ORNL Triangular pads 16 hexagonal towers proposed by ORNL fit nicely in circles around beam-pipe uses more Si surface of cylindrical ingot Triangular pads Voltage amplifier and readout Individual layer

Detector Design-III 17 W absorber + Monolithic pixel sensor (Utrecht, Bergen) MIMOSA chips (digital readout) are promising to use. Development has been started. Personal interests as preshower counter and hybrid with pads CMOS wafer including thin sensitive volume and electronic layers charge from traversing particles collected at diodes

MAPS Open Questions and Possible Specs 18 pixel size: current designs ≈ 20 µm for FoCal 100 µm? charge collection? data volume: zero suppression? full frame readout? possible option: GBTX serializer per layer, 4.8 GB/s output via twisted pair power consumption: currently ≈90 mW/cm2 sensor ≈ 60 kW total tolerable? readout time: 40 µs total RO time (200 rows) has to be shortened simulations on going limit near ~10 us option worked out

MAPS readout Layer 0 BackBox of Tower 0 Layer 23 19 E-Link TLC12 Clock ca. 15cm twisted pair cables @ 4,8 GHz 19 E-Link FoCal Layer_0 0-11 16 GBLD_0 TLC12 MAPS_0 Clock GBTX Ribbon fiber cable GBLD_23 4.8 Gbit Fiberlink 16 MAPS_15 Serial/ Deserial Vcsel Driver Data 12-23 TLC12 Control/Trigger Ribbon fiber cable I²C/ JTAG GBTSCA 24 GBTIA Slow Control Temp. Buffer 4.8 Gbit Fiberlink Layer 0 Receiver E-Link FoCal Layer_23 To other layers 16 MAPS_368 BackBox of Tower 0 Clock GBTX 16 MAPS_383 Serial/ Deserial Data E-Link uses SLVS: Scalable Low Voltage Signaling (Low power / low voltage LVDS) Control/Trigger I²C/ JTAG GBTSCA All GBT chips are part of CERN Project (Gigabit receivers) Slow Control Temp. MAPS readout Layer 23

Plan in 2011 ~Mar. in 2011: ~Oct. in 2011: ~Nov. in 2011: Release “Letter of intent” to the ALICE ~Oct. in 2011: One tower (W+Si pad/strip?) assembling completed ~March: Summing board/Backboard ~April/May: Tungsten, Jig Completed ~April: 2nd ASIC submission ~July: Assembling completed. 3rd ASIC submission ~Sept/Oct: ASIC production (2nd version or 3rd version of ASIC) and mount. Partial W+Si pixel ~Nov. in 2011: Beamtest @ PS and SPS One tower W+Si pad & partial W+ MAPS Si pixel Beamtime for FoCAL was already requested to the ALICE.

Possible FoCAL Spec with fine pads 21 Design 1 2 3 4 Width [m] 1.5 Area [m²] 2.25 layers 30 21 total area [m²] 120 68 47 W thickness [mm] weight [kg] 6,966 3,918 2,743 pad size [mm] 5 10 pads per layer 160,000 90,000 22,500 total pads 4,800,000 2,700,000 1,890,000 472,500 total chips 37,500 21,094 14,766 3,691

Cost Estimation 22 Design 1 2 3 4 [k€] support MiniFrame 1,000 Tungsten 871 490 343 unit mechanics 500 281 cooling 197 silicon sensors 12,000 6,750 4,725 4725 chips 1,875 1,055 738 185 electronics 1,500 844 591 148 cables and connections 9,600 5,400 3,780 945 total 27,985 16,101 11,655 7,824 Current R&D cost: CNS (200k? Euro funded) Czech (Prague) will request ~2 M Euro for FoCAL project.