Giga-Scale System-On-A-Chip International Center on System-on-a-Chip (ICSOC) Jason Cong University of California, Los Angeles Tel: 310-206-2775, Email: cong@cs.ucla.edu (Other participants are listed inside)
Background: “Double Exponential” Growth of Design Complexity C1: complexity due to exponential increase of chip capacity More devices More power Heterogeneous integration, …… C2: complexity due to exponential decrease of feature size Interconnect delay Coupling noise EMI, …… Design Complexity C1 x C2 Jason Cong
Motivation: Productivity Gap 10,000,000 100,000,000 1,000,000 10,000,000 58%/Yr. Complexity growth rate 100,000 1,000,000 Logic Transistors/Chip (K) Transistor/Staff-Month 10,000 100,000 1,000 10,000 21%/Yr. Productivity growth rate 100 x x 1,000 x x x x x 10 x 100 1 10 1998 2003 Chip Capacity and Designer Productivity Jason Cong Source: NTRS’97
Project Summary Develop new design methodology to enable efficient giga-scale integration for system-on-a-chip (SOC) designs Project includes three major components SOC synthesis tools and methodologies SOC verification, test, and diagnosis SOC design driver – network processor Jason Cong
Current Research Team US Taiwan China UCLA: Jason Cong UC Santa Barbara: Tim Cheng Taiwan NTHU: Shi-Yu Huang, Tingting Hwang, J. K. Lee, Youn-Long Lin, C. L. Liu, Cheng-Wen Wu, Allen Wu NCTU: Jing-Yang Jou China Tsinghua Univ.: Jinian Bian, Xianlong Hong, Zeyi Wang, Hongxi Xue Peking Univ.: Xu Cheng Zhejiang Univ.: Xiaolang Yan Several new faculty members in the 7 institutions Guest members from National University of Singapore, Purdue Univ., UCLA (EE Dept), and UT Austin Jason Cong
Thrust 1 -- SOC Synthesis Environment/Methodology (Led by Jason Cong) Design Spec VHDL/C VHDL/C Co-Simulation Design Partitioning ASIC Synthesis Interconnect-Driven High-level Synthesis Code Generation for Retargetable Compiler and Assembler Generator DSP Synthesis and Optimization FPGA Synthesis and Technology Mapping Synthesis for IP Reuse Physical Synthesis for Full-Chip Assembly Embedded Processors DSPs Embedded FPGAs Customized Logic Jason Cong
Highlights of Accomplishments Novel microarchitecture and system methodology for multi-cycle on-chip communication ISPD’03, ICCAD’03, DAC’04, T-CAD Optimality study of large-scale circuit placement ASPDAC’03, ISPD’03, ICCAD’03, T-CAD Floorplanning with interconnect planning About 30 papers published in DAC, ICCAD, ISPD, ASPDAC, ISCAS and Transactions P/G Network Analysis & Optimization ICCAD’01, T-CAD, ASPDAC’04 Parasitic R/L/C extraction ASPDAC, ASICON and IEEE Transaction on MTT Jason Cong
Thrust 2 -- SOC Verification, Test, and Diagnosis (Led by Tim Cheng) Verification and Testing Testing and diagnosis for heterogeneous SOC Enabling techniques for semi-formal functional verification Self-testing using on-chip programmable components Self-testing for on-chip analog/mixed-signal components Automatic/semi-automatic functional vector generation from HDL code Scalable constraint-solving techniques Integrated framework for simulation, vector generation and model checking New test techniques for deep-submicron embedded memories Jason Cong
Highlight of Accomplishments Developed and released ATPG-based SAT solvers for circuits DATE2003, DAC2003, ICCAD2003, HLDVT2003 and ASPDAC2004 A new Statistical Delay Testing and Diagnosis framework consisting of five major components DAC’02, ICCAD’02, DATE’03, DAC’03 On-Chip Jitter Extraction for Bit-Error-Rate (BER) Testing of Multi-GHz Signal ASPDAC2004 and DATE2004 Jason Cong
Thrust 3 – Design Driver: Network Security Processor (Led by Prof. C. W. Wu & Xu Cheng) Applications: IPSec, SSL, VPN, etc. Functionalities: Public key: RSA, ECC Secret key: AES Hashing (Message authentication): HMAC (SHA-1/MD5) Truly random number generator (FIPS 140-1,140-2 compliant) Target technology: 0.18m or below Clock rate: 200MHz or higher (internal) 32-bit data and instruction word 10Gbps (OC192) Power: 1 to 10mW/MHz at 3V (LP to HP) Die size: 50mm2 On-chip bus: AMBA (Advanced Microcontroller Bus Architecture) Jason Cong
Highlights of Accomplishments Security processor – encryption module Secret key encryption module Operations: Matrix operations, manipulation AES cryptography 32-bit external interface 58K gates Over 200MHz clock Throughput: 2Gbps Support key length of 128/192/256 bits Microprocessor -- Unity Processor Used in over 7,000 NetPCs Jason Cong
International Collaborations Joint NSF/NSC workshop in Aug. 1999 on SOC (Hsin-Chu, Taiwan) 1st team preparation meeting for the proposed center in Jan. 2000 (Yokohama, Japan) 2nd planning meeting held in April 2000 (Hawaii, US) 3rd planning meeting in Aug. 2000 (Chengde, China) Proposal submitted to NSF in Aug. 2000 and funded in Dec. 2000 Workshops March 30-31, 2001 in Taipei, Taiwan. June 23-24, 2001 in Los Angeles, USA August 31-September 1, 2001 in HangZhou, China March 28-29, 2002, National Tsing Hua University, Hsinchu, Taiwan August 20-21, 2002, Peking University, Beijing, China November 15-16, 2002, University of California, Santa Barbara March 27-29, 2003, National Taiwan University, Taipei, Taiwan December 19-21, 2003, Yunnan University, Kunming, China Jason Cong
Publications 220 research publications up to this point 67 in top conferences/journals in the field (DAC, ICCAD, DATE, ASPDAC, ITC, FPGA, ISLEPD, T-CAD, TODAES, etc.) Jason Cong
People & Education Many interactions among participants from different institutes Two new IEEE fellows: Prof. Xiaolang Hong, Tsinghua Univ. Prof. Cheng-Wen Wu, National Tsing Hua Univ. Involved many young faculty members and researchers Trained an army of graduate students Jason Cong
Complexity Management for Future Micro and Nano Systems Higher level of abstraction (without losing physical reality) Reliability and reconfigurability Fundamental algorithms for future design automation tools of micro and nano systems Education Jason Cong
Participants US Taiwan China Japan ?? UCLA and UCSB National Tsing Hua Univ. National Taiwan Univ. ?? China Tsinghua Univ. ?? Japan ?? Jason Cong