A Partial Reconfiguration Controller for Altera Stratix V FPGAs

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A Partial Reconfiguration Controller for Altera Stratix V FPGAs Zhenzhong Xiao, Dirk Koch, and Mikel Lujan, University of Manchester, UK

Background: Altera PR Flow Altera PR flow is very similar to the Xilinx flow using proxy logic for the connection with the PR modules Advantage in Altera FPGAs: PR modules are not bound to clock regions Configuration mask defines what parts of the FPGA can be configured Message: within the next one to two years we will see FPGAs capable to host far beyond 100 fully featured soft-core CPUs!!!

Altera Configuration Masks Configuration masks can be static or part of the PR bitstream (the tools take care about this) a) No columns of PR regions overlap: no mask needed in the bitstream b) Some or all columns of the PR regions overlap: Configuration masks added to the PR bitstream Configuration masks impact configuration storage and configuration latency! Message: within the next one to two years we will see FPGAs capable to host far beyond 100 fully featured soft-core CPUs!!!

Measuring Impacts on the Bitstream Size size 6400 ALMs size 3600 ALMs Utilization Mode 80 x 80 120 x 54 54 x 120 60 x 60 120 x 30 30 x 120 30% mask 15,794 20,508 11,343 12,007 20,529 6,720 plain 8,720 12,633 6,442 6,707 4,046 60% 15,829 22,274 11,375 12,015 20,924 6,920 8,723 12,632 6,444 90% 15,766 23,289 11,436 12,068 23,284 6,958 12,634 Message: within the next one to two years we will see FPGAs capable to host far beyond 100 fully featured soft-core CPUs!!!

A Decompressing Configuration Controller Module wrapper Up to 77% saving in bitstream size Much better than the compression mode of Altera’s EPC configuration memories Message: within the next one to two years we will see FPGAs capable to host far beyond 100 fully featured soft-core CPUs!!!