FTK: update on progress, problems, need - 2011 Activities - Financial situation - Manpower Mel & Paola - USC 20-1-2010

Workpackages AMchip Boards Integration: Vertical Slice → Demonstrator → Phase I system Board integration, diagnostics, tests Integration into TDAQ, DCS Connection to L2 and detector High level system performance monitoring FTK Performance: simulation studies and checks with data Mel & Paola - USC 20-1-2010

Schedule for the first submission - 65 nm MPW CHIP 12 mm2 AMCHIP: 2011 work Plan Develop two full-custom cells (pattern and majority logic) and the standard-cell project (control logic) started modifications to the control logic design to take into account the new “don’t care” feature and 8 input buses instead of 6. New pin assignment has been done. (F. Crescioli) Design of the full custom pattern cell individual elements are in an advanced status (schematics, analog simulation). To be connected to produce a super-cell of 32 patterns. (M. Beretta) Majority logic cell: Verilog implementation is ready, timing simulation very promising (J. Hoff). Test of standard cell and full custom logic integration: put together two simple pieces and perform all the steps up to the final DRC and LVS checks. Done successfully. To be repeated with the specific Pattern cell (A.Stabile). Test vector generation by a high level C++ program – started modification to the logic to take into account the new “don’t care” feature and 8 input buses. (I.Sacco) Production of a Model of custom cells – to be done Combine all parts and simulate intensively the whole project, before and after placing & routing - to be done Final checks (DRC, LVS) and timing analysis before submission - to be done Schedule for the first submission - 65 nm MPW CHIP 12 mm2 TSMC offers at least 1 MPW Run per month for the 65 nm technology. Summer : have the design ready with intensive simulation Autumn: submission of the chip for an MPW run Mel & Paola - USC 20-1-2010

Schedule for the first prototype Boards: Boards: 2011 workplan for each board (all boards in parallel) Define specifications: ongoing for USA boards (Shochet, Bogdan, Neubauer, Liu) Design the board (schematics): ongoing for Italian boards: DF mezzanine, AMBoard, LAMB (Andreani, Piendibene, Annovi, Beretta, Giannetti, Lanza) Design the Firmware ongoing for Italian boards (Andreani, Piendibene, Magalotti, Bevacqua, Annovi). Simulate the logic - to be done Optimize Layout, Placement and Routing - to be done Analog Simulation of critical nets – to be done Prototype production and assembly - to be done Schedule for the first prototype Boards: Italy: Summer ‘11: design ready – intensive simulation Autumn ‘11: PCB production US: Winter ’12: design and simulation complete including firmware Spring ’12: prototype board production Dual-output HOLA: Chicago design near completion; prototype testing in May, production readiness review in June, production for December installation. Mel & Paola - USC 20-1-2010

Vertical slice: 2011 workplan Setup of a “5kW” test stand for boards/cooling tests (Piendibene, Giannetti): PCB boards able to power 128 Amchips done, to be assembled (ordered chips, available in February). Crate able to provide 5 kW to the boards available in January Test of new board & production of ~5 of them - to be done 2011 Development of global test of EDRO+AMBOARD (Villa, Giorgi, Annovi, Crescioli, Piendibene, Magalotti) Transfer CDF tests into TDAQ framework done Global control software and tests ready to be done (Autumn) Final crate choice: discussing custom solutions for J1 access from both rear and front sides. FTK connection to L2, new possibility under study: use of a ethernet FTK output to go directly to a CPU (Negri). Mel & Paola - USC 20-1-2010

Simulation studies & checks on data: manpower needed FTKsim: a production version for Atlas studies and a development version for testing new ideas FTKsim for the barrel ready to become a production version for use by Atlas: G.Volpi will present at the next simulation group meeting the FTKsim needs. Development FTKsim version (Melachrinos, Cheng, Volpi): Implement IBL: (a) cluster optimization (b) best layer choice for the 1st FTK step Forward/backward optimization Best use of the “don’t care feature” (variable resolution pattern recognition) Study of FTK efficiencies, fakes, and robustness (Tuggle, Tang, Webster) New HLT selections based on FTK track use (Boveia): develop new b, tau, lepton selections based on FTK tracks – manpower needed Simulation of FTK on real data. Comparison to generator data (efficiencies, fakes) Check MC FTK tracks with real FTK tracks. Reconstruct Z→bb, Z→ using FTK tracks (real data); Reconstruct mass peaks for hadronic B decays using FTK tracks (real data). Reconstruct dibosons with lepton isolation based on FTK tracks (real data). Mel & Paola - USC 20-1-2010

Financial-political issues US: January 27 – submission of MRI proposal for FY12-16 Funds for FY11 requested from US ATLAS Fermilab applying to join Atlas under serious discussion Italy: 2011 money available, signed a letter for MRI application saying that $1,335,903 will be provided by Italy if MRI is approved Japan: approval expected in April?

Conclusions A lot of work has to be done hardware work is going on help is needed for early FTK studies on data Mel & Paola - USC 20-1-2010