Front-end Electronic for a neutrino telescope : a new ASIC SCOTT Genova 9-10-11 April 2008 Fabrice Guilloux on behalf of IRFU – Saclay

The best choice for PMTs readout From Scale to Scott Status of the design study @ Nikhef 16 november 2007 This talk The best choice for PMTs readout Up to date Processing DAQ ARS feedback Asic SCALE From Antares : + Fulfills Physic’s requirements + Fits to DAQ Analog processing Digitization Digitization TOT Digital Processing Evaluation Phase Digitization ADC Digital Processing 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Signal reconstruction From Scale to Scott Principle t1 t2 t3 t4 t5 t6 Time Time Threshold 1 Threshold 2 Threshold 3 Amplitude Amplitude PMT signal Output Signal reconstruction Main results from real PMT output signals study Arrival time [ok] Easy walk correction with only 4 points Charge reconstruction [ok] DE/E < 10% for a dynamic range < 80 PE with 8 thresholds Limited by PMT output current saturation for the dynamic range DE/E < 10% with 4 thresholds for a dynamic range < 10 PE and DE/E > 10% for a dynamic range > 10 PE 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Relationship between TOT & Tpeak From Scale to Scott Time reconstruction Error in peaking time reconstruction Relationship between TOT & Tpeak Main results from real PMT output signals study Arrival time [ok] Easy walk correction with only 4 points Charge reconstruction [ok] DE/E < 10% for a dynamic range < 80 PE with 8 thresholds Limited by PMT output current saturation for the dynamic range DE/E < 10% with 4 thresholds for a dynamic range < 10 PE and DE/E > 10% for a dynamic range > 10 PE 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

New ASIC : Synthesis of the two previous concepts From Scale to Scott Scale + Optimize for « SPEs » (Most frequent events). + Self trigged and Timestamp on chip : no external data treatment + On-chip “derandomization” - Complex analogue part : asynchronous memory + multi-channels ADC+ charge reconstruction. - Need of an extra-channel for non SPE event (waveform) ToT Asic [Comparators only] + Fast data conversion to digital + Completely synchronous - Fast link between the ASIC and the FPGA  high power consumption and link problems (same PCB) - Number of thresholds limited to match with DAQ data rate New ASIC : Synthesis of the two previous concepts 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

From Scale to Scott Scott : Sampled Comparators autOtrigged & Tagged in Time 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : Functionalities & Performances 1/4 Comparator + Sampler + Converter DAC : 15 flexible thresholds : 1V@10bits  LSB ~ 1mV High Precision Continuous time sampling in a circular buffer: (2x16 bits)x15 No dead time Fine timestamp : Tech = 16/Fck Max ~ 0.5nsrms Data compression : from thermometer to binary code Low data rate Ex : Fck = 50MHz Fsample = 800MHz  Tsample = 1.25ns 40 ns T0 : Coarse time 16 bits Max T0 = 1.3ms 1.25 ns 20 ns 3 discriminators (instead of 15) 0 0 0 0 0 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Amplitude + fine time : 2 x 16 x 4 bits Coarse time : 16 bits SPE : 144bits 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : Functionalities & Performances 2/4 Digital fifo memory Zeros Suppress : data are stored in memory only if L0 is high Low data rate Common treatment SPE and Waveform 1 path ! Fifo ~ 2.3k bits: Fck = 50 MHz  16 SPEs or 640ns WF Derandomization Ex : SPE event Ex : Waveform event, fck = 50 MHz M1 M2 M1 M2 M1 M2 Initial conditions 15 thresholds [4 thresholds] Clock : fck = 50 MHz Hits rate : 250khit/s 4 bits Output Transfer rate Nb bits / SPE : 144 [80] bits Data rate : 36 [20] Mbits/s Readout frequency : 9 [5] MHz Discri 1 Discri 2 Discri 3 120ns Time Stamp M1 M2 Almost empty memory saved 16 bits 4 x 16 bits 4 x 16 bits Time Stamp M1 M2 FIFO DT ~ 0.5nsrms 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : Functionalities & Performances 3/4 No difference between single PE and multi PE « single PE » events « multi PE » events TimeStamp 1 TimeStamp 2 TimeStamp 3 TimeStamp 4 TimeStamp 5 TimeStamp 6 M1 M2 M1 M2 M1 M2 M1 M2 M1 M2 M1 M2 Discri 1 Zeros Supress Discri 2 Discri 3 Coarse Time Coarse Time Time Stamp 1 M1 M2 Time Stamp 4 M1 M2 Fine time + Amplitude Fine time + Amplitude Time Stamp 3 M1 M2 Time Stamp 5 M1 M2 Time Stamp 6 M1 M2 FIFO FIFO Size of buffers optimized for single PE 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : Functionalities & Performances 4/4 Simple function foreseen in the SoC Second level zeros suppress  fine time recovery Ex : Second level zero suppress Index of first non empty cell = fine time 1 2 3 4 5 1st year xth years Slicing window [examples 16 memories  20 ns @ 50 MHz 8 memories  20 ns @ 25 MHz] 16 thresholds  144 bits/SPE Time precision ~ 0.5 ns rms : Nb bits / SPE = 84 bits @ 50MHz Time precision ~ 1 ns rms : Nb bits / SPE = 52 bits @ 25MHz [4 thresholds]  Time precision ~ 0.5 ns rms : Nb bits / SPE = 52 bits @ 50 MHz 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : Advancement Design Status Design Planning Test Planning: Schematic simulation of the complete ASIC [top to bottom] Schematic design in progress Design Planning Submission by the end of the year Test Planning: Design of a new test board Integration with the Km3Net new DAQ framework (SoC & Software = WP4) XILINX ML405 Board Pseudo-Clock Board XC4FX20 device (PPC405@300MHz, 1 Gb/s Ethernet link) 128 MB DDR SDRAM 8 MB Flash Adaptation Board CPU Slot OM 2 OM 1 3 ARS Boards OM 0 Will be upgraded with a XC4VFX40 ANTARES LCM Crate 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : complete DAQ scheme DAQ readout design Slow Control Digital Data Clocks Scott Ethernet Gigabit Scott SoC To Shore Point to point connection … All the electronic in a « Master » sphere (with a PMT or not) Thank you for your attention 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Backup 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting

Scott : complete DAQ scheme Temperature constrains Power DTemperature 4.7 W Non measured 8.5 W 18° C 19 W 38° C 10/04/2008 Front End Electronics readout Fabrice Guilloux / Eric Delagnes Genova : WP3 Meeting