Pid session TDC-based electronics for the CRT Christophe Beigbeder December 1st 2009

Distributed on 4 receiver boards Gary Varner’s module PMs side : 4*16 PM outputs Distributed on 4 receiver boards Christophe Beigbeder December 1 2009

Powers and cools down the complete module. Motherboard : Powers and cools down the complete module. Receives the 64 channels from the receiver boards. Packs the events and sends them to the control room over optical links. Christophe Beigbeder December 1 2009

We can use Gary’s motherboard and only develop the receiver board We are facing some problems to develop an instantaneously CRT pluggable module Mechanically, this study is quite obvious. For the electronics point of view: We can use Gary’s motherboard and only develop the receiver board The Interface to the DAQ is done but we need the protocol between the receiver board and the mother board (embedded in the 2 PGAs). Or we can design a new complete module We need to know the DAQ protocol. We need to know the data formatting. We need to know the serial protocol for the link and be compatible with the receiver . We need to develop our own software application in the existing environment. -> In any case we need a close collaboration with Gary for the firmware and the software. Christophe Beigbeder December 1 2009

The other solution is to build our own system : A module mechanically compatible with the PM footprint and the available space. An electronics board and a DAQ system independent from the existing one. -> We could bring to SLAC a complete system including DAQ which has already been fully tested. -> Discussion with Jerry and Veronique on how to prepare the test in Orsay. Can we buy/borrow PMs ? Christophe Beigbeder December 1 2009

New proposal for a CRT module Fit the module size Sample and hold Acquisition on PC ADC TDC x16 x4 FPGA USB 16 USB hub Copper to optical transceiver Discriminator TDC/ time stamper100 ps Christophe Beigbeder December 1 2009

Conclusion A complete design of a new module seems to be the most reasonable solution. The analog part of the scheme is tricky and needs more investigations. A collaboration with LPNHE Paris 6 will start on this part as soon as possible. The responsibility for the future front-end ASIC will be shared between LPNHE and LAL. The TDC (time stamper) already presented here will be used for the module. The low rate of the cosmic rays is compatible with his architecture. We will launch the study on the high rate version as soon as we can get manpower at LAL to collaborate with CAEN’s lab. The complete acquisition chain will be fully tested at Orsay before coming to SLAC early next year. Christophe Beigbeder December 1 2009