MOS Capacitance Unit IV : GATE LEVEL DESIGN VLSI DESIGN 17/02/2009

Poly/metal wire capacitance Two components: parallel plate; fringe. fringe plate 17/02/2009 VLSI Design

Metal coupling capacitances Can couple to adjacent wires on same layer, wires on above/below layers: metal 2 metal 1 metal 1 17/02/2009 VLSI Design

Parasitic Elements So far, we’ve concentrated on getting circuit elements that we want for digital design Transistors Wires Parasitics - occur whether we want them or not Capacitors Resistors Transistors (bipolar and FET) 17/02/2009 VLSI Design

Basic transistor parasitics (1/2) Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance. 17/02/2009 VLSI Design

Basic transistor parasitics (2/2) Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. Cgs = Col W Gate/bulk overlap capacitance. 17/02/2009 VLSI Design

Capacitance (1/2) Transistors Depends on area of transistor gate Depends on physical materials, thickness of insulator Given for a specific process as Cg Diffusion to substrate Sidewall capacitance - capacitance from periphery bottomwall capacitance - capacitance to substrate Given for a specific process as Cdiff,bot, Cdiff,side 17/02/2009 VLSI Design

Capacitance (2/2) Metal to substrate Parallel plate capacitance is dominant Need to account for fringing, too Poly to substrate Parallel plate plus fringing, like metal Gotcha: don’t confuse poly over substrate with gate capacitance Also important: capacitance between conductors Metal1-Metal1 Metal1-Metal2 17/02/2009 VLSI Design

Transistor gate parasitics Gate-source/drain overlap capacitance: gate source drain overlap 17/02/2009 VLSI Design

MOS Capacitance Accumulation C0 = esio2e0 A / tox Depletion Cdep = esie0 A / d 17/02/2009 VLSI Design

MOS Capacitor Inversion 17/02/2009 VLSI Design

MOSFET Capacitance Depletion Capacitance: Cdep = eSi e0 A/d, eSi = 12, d = depletion layer depth Total C between gate & substrate Cgb C0 in series with Cdep Cgb = C0 Accumulation Mode Cgb = C0 Cdep /(C0 + Cdep) Depletion Mode 17/02/2009 VLSI Design

MOSFET Capacitance In inversion, there is a limited supply of charge carriers to the inversion layer, so it cannot track rapid voltage changes. Dynamic C is the same as for depletion Cgb = C0 {f < 100 Hz} = C0 Cdep/(C0 + Cdep)=Cmin {high f } 17/02/2009 VLSI Design

MOSFET Capacitances Logic Gate load capacitance has 3 C’s in parallel between gate output & substrate: Transistor gate capacitance (of other gate inputs connected to this gate output) Diffusion capacitance of transistor drains connected to gate output Routing capacitance of wires connected to the output 17/02/2009 VLSI Design

MOSFET capacitances MOS capacitances have three origins: The basic MOS structure The channel charge The pn-junctions depletion regions 17/02/2009 VLSI Design

Capacitances Cgs, Cgd = gate to channel capacitances, lumped at source & drain Csb, Cdb = source & drain diffusion capacitances to bulk 17/02/2009 VLSI Design

Approximation of Intrinsic MOS Capacitances 17/02/2009 VLSI Design

Capacitance Calculation Off region, Vgs < Vt, no channel so Cgs = Cgd = 0 Cgb = C0 Cdep C0 + Cdep Non-saturated (linear) region Vgs = Vt Vds Constant depletion layer depth, channel forms, Cgs, Cgd become significant Cgd = Cgs 1 e0 eSiO2 A 2 tox Cgb 0 ( ) 17/02/2009 VLSI Design

Capacitance Calculation (cont’d.) Saturated region Vgs – Vt < Vds Channel heavily inverted, drain pinched off, Cgd = 0 Cgs = 2 e0 eSiO2 A 3 tox ( ) 17/02/2009 VLSI Design

Long Channel C Variation 17/02/2009 VLSI Design

Short Channel C Variation 17/02/2009 VLSI Design

Saturation Capacitance Cgd = finite in saturation due to channel side fringing fields between gate & drain Approximate Cg as C0 = Cox A Cox = e0 eSiO2/tox 17/02/2009 VLSI Design

My name should not be prominent …. My ideas that I want to be realized…. --- Swami Viveka Nanda 17/02/2009 VLSI Design