Copied with Permission from prof. Mark Faust @ PSU ECE ECE 171 Digital Circuits Chapter 9 Hazards Herbert G. Mayer, PSU Status 5/2/2016 Copied with Permission from prof. Mark Faust @ PSU ECE

Syllabus Glitches and Hazards Static Logic Hazards Static Function Hazards Dynamic Hazards Hazard Exercises 1-5 Decoders Multiplexers References

Glitches and Hazards So far we assumed: steady state of a circuit Steady state is equivalent to having “waited” a long time for signals to settle Long time meaning: more than 1 cycle for clocked-, or longer than signal propagation for un-clocked circuits In practice, the actual time for a signal to propagate to the output gate can be long, and the time may depend on, which path that signal has taken Depending on such paths, outputs may experience an unintended pulse, AKA glitch Glitch means: though the steady state produces the correct signal, an opposite signal occurs momentarily Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Glitches and Hazards Hazard means the condition for a glitch exists It doesn’t mean something unexpected actually occurs each time (think of road hazard) Existence of hazard leaves open the possibility that a bad signal doesn’t occur at all during this execution It means, the problem can occur, based on input signal combinations, and on actual signal path taken The circuit designer must identify, whether hazards are acceptable or not If hazards are not acceptable, a designer analyzes the circuit, introduces logic to eliminate all hazards, e.g. via consensus terms Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Glitches and Hazards Glitch: Wrong signal in a circuit due to unequal delay paths; this is the manifestation of a hazard Logic Hazard: Is a glitch when one input changes. Can be removed by adding logic: AKA consensus terms Function Hazard: May cause glitch when two or more inputs change at once. Cannot generally be removed by adding logic Static Hazard: Occurs when output of the circuit is supposed to be constant. There are 2 kinds: unexpected 0, or unexpected 1 Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths. Dynamic Hazard: Occurs when output of the circuit changes unexpectedly more than once for a single input change Function and Logic Hazards can be Static or Dynamic

Glitches and Hazards Definition: A static-1 hazard is an unexpected 0 output, generated by a pair of input combinations such that: a.) the two inputs differ by just 1 variable, b.) both combinations produce a 1 output signal, yet c.) an unwanted 0 signal occurs during the single input transition Definition: A static-0 hazard is an unexpected 1 output, generated by a pair of input combinations such that: a.) the two inputs differ by just 1 variable, b.) both combinations produce a 0 output signal, yet c.) an unwanted 1 signal occurs during the single input transition Definition: A dynamic hazard is the possibility of an unexpected change of the output signal more than once as a result of a single input signal change Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Quick Check 1.) Some circuit C1 contains a static-1 hazard. C1 is activated and after some defined time, it terminates. Does a problem occur in C1? 2.) Some circuit C2 contains a static-0 hazard. C2 is activated and after some defined time, the circuit terminates with a glitch occurring; i.e. an unexpected ‘1’ signal was generated. Did an actual problem occur in C2’s output? Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Reminder SoP: Sum of Product terms PoS: Product of Sum terms Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Static Logic Hazards Single input changed. Resulting output should have remained constant: 1 in case(a). 0 in case(b). However, a glitch appeared before the output settled back to its correct level Two-level SoP circuits may see static-1 hazards Two-level PoS circuits may see static-0 hazards

Static-1 Hazard with SoP

Static-1 Logic Hazard Let’s look in detail at how a static logic hazard might arise, how it would manifest itself as a glitch and what you can do about it. Mention simulation Also mention that the glitch may not make a difference – synchronous design which you’ll learn later (for now, just know that we may only “look” at the output after a certain “settling” time. Students draw minimized circuit in class, SoP form: And- and Or-gates OK, better even Nand-gates

NAND/NAND Implementation Static-1 Logic Hazard Consider inputs ABC 111 time t1 110 time t2 1 1 Let’s look in detail at how a static logic hazard might arise, how it would manifest itself as a glitch and what you can do about it. Mention simulation Also mention that the glitch may not make a difference – synchronous design which you’ll learn later (for now, just know that we may only “look” at the output after a certain “settling” time. NAND/NAND Implementation

Observe Carefully: If first input at time t1 is: A B C = 1 1 1, the output F1 will be 1, due to nand-gate with inputs B C Then at time t2 the input changes to A B C = 1 1 0 Output F1 again is 1, due to nand-gate with inputs A C’, but the length (and thus the length of time) for the input path with signal C’ is longer, due to the inverter; may be critical! In some instances that may be a sufficient delay to create a brief static 1 hazard, AKA 0 glitch 1 hazard alluding to: signal should be 1 but isn’t Static alluding to: signal should be 1 before, should be 1 after, but there is a wrong 0 value! Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

NAND/NAND Implementation Static-1 Logic Hazard Consider inputs ABC 111 110 1 1 Let’s look in detail at how a static logic hazard might arise, how it would manifest itself as a glitch and what you can do about it. Mention simulation Also mention that the glitch may not make a difference – synchronous design which you’ll learn later (for now, just know that we may only “look” at the output after a certain “settling” time. NAND/NAND Implementation

Detect, Eliminate Static-1 Hazard

Countermeasure To avoid this type of hazard: With input transition 111 -> 110, output signal F1 should stay 1: was 1 initially, should remain 1 Yet the “second 1” may arrive just a bit late: longer path Add 3rd signal path (consensus term) that covers areas of 1s with further option to generate 1 signal: AB Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Detect, Eliminate Static-1 Hazard

Static-0 Hazard with SoP

Static-0 Hazard SoP Form for 0s: F1’ = . . . Students!! Implement a hazard-free circuit for the 0s of the previous function using NOR gates SoP Form for 0s: F1’ = . . . Students!! Students write F1( A, B, C ) in SoP form, for 0s

Static-0 Hazard SOP Form for 0s: Implement a hazard-free circuit for the 0s of the previous function using NOR gates SOP Form for 0s: Hazard occurs at boundary of 2 terms, both of which deliver the same signal of interest, 0 here, at different times Consensus term needed to deliver same signal, 0 here, if the other 2 terms may not “agree” about timing To avoid a logic 1 glitch

Static-0 Hazard Where is a critical boundary? Look for: products grouped together! Look for: logically adjacent terms in K-map Add new term covering some ‘1’ (ones) of both, adjacent terms Is redundant for signal-generation, but adds needed value that otherwise might get lost, due to glitch Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Static-0 Hazard Students, which term is to be added? One that covers 0s, when 2 adjacent terms should be 0, but happen to become temporarily 1 Note: even gates on the same IC will not have exactly identical propagation delays and then of course there are different “wire”/trace path lengths.

Needed Cover Term Included Static-0 Hazard Implement a hazard-free circuit for the 0s of the previous function using NOR gates SOP Form for 0s Needed Cover Term Included

Static Function Hazards Easy to Handle! The bad side-effect of multiple input signals changing and producing an unwanted signal cannot always be removed by adding logic to the existing circuit; Solution: design new logic!

Hazard Example

Hazard Example Given the K-Map for function Haz() below: Write function Haz() in SoP form Identify where hazards exist Devise a hazard-free function Haz’() equivalent to Haz()

Hazard Example Assuming Haz() = a c’ + b c The hazard arises between cells: a b c’ d and a b c d Add new term a b d, so: Haz’() = a c’ + b c + a b d Students, is that a correct fix? Students, is that THE simplest form to avoid the hazard?

Hazard Example Assuming function Haz() = a c’ + b c The hazard arises between cells: a b c’ d and a b c d Add simpler term a b, so: Haz’() = a c’ + b c + a b

Dynamic Hazard

Dynamic Hazards Dynamic hazards occur in multi-level circuits with multiple paths, each having different delays from input to output Do not occur in 2-level SOP (or POS) implementations Requires these further timing choices, each with differing timings, to cause multiple glitches

Implementations for Complex Functions and Their Delays

Implementations for Complex Functions and Their Delays (a) improved: do all signals A B C have the same number of delays to output F9? (b) improved: how many differing delays do signals X Y Z exhibit in improved circuit F10’? (b) improved: What is F10? (we are given only F10’) (b) improved: Is F10’ improved a good design? (c) prove: all 3 F11 are the same logic function (c ) how many differing delays do signals A B C D exhibit in the third (lowest) circuit F11?

Hazard Exercises

Hazard Exercise1 Using And gates, Nand gates, OR gates, and inverters gate inputs or outputs may also be inverted internally, via inversion bubbles directly at input or output pins Build circuit for F( A, B, C, D ) = B’D’ + ABC’ + ACD Step 1: Draw the circuit for the function of 4 variables F( A, B, C, D ) = B’D’ + ABC’ + ACD in SoP form No need to minimize We use this same circuit in Step 2

Hazard Exercise1 Solution to Step 1, others possible: Circuit for F( A, B, C, D ) = B’D’ + ABC’ + ACD in SoP form

Hazard Exercise1 Step 2: Using function F( A, B, C, D ) = B’D’ + ABC’ + ACD, draw the Karnaugh map for F() Identify where static hazards can occur Add terms to remove these hazards and design a new hazard-free logic function HF()

Hazard Exercise1 Hazards for F() = B’D’ + ABC’ + ACD can occur at color marked boundaries To be added: AC’D’ + ABD + AB’C

Hazard Exercise1 So the hazard free function HF() is: HF( A, B, C, D ) = B’D’ + ABC’ + ACD + AC’D’ + ABD + AB’C

Hazard Exercise2 Explain “static-1 hazard” in a sum-of-products circuit: What causes such a hazard? Will a correctly designed two-level circuit have static-1 hazards? How can such hazards be prevented? What (almost) synonym for hazard is used colloquially, though incorrectly?

Hazard Exercise2 Explain “static-1 hazard” in a sum-of-products circuit: What causes such a hazard? Different propagation delays through circuit by paths of differing lengths Will a correctly designed two-level circuit have static-1 hazards? No, because all paths have the same timing How can static-1 hazards be prevented? By adding further circuitry that solves the timing difference via additional steps in paths; name: consensus path What (almost) synonym for hazard is used colloquially? Glitch, but keep in mind they are different! Glitch is actual occurrence But ECE 171 students will avoid such sloppy habits 

Hazard Exercise3 Question1: Explain “dynamic hazard” in a two-level sum-of-products circuit. Question2: Can they occur in two-level SoP circuit?

Hazard Exercise3 Question1: Explain “dynamic hazard” in a two-level sum-of-products circuit Answer1: A dynamic hazard is the repeated change of the output signal caused by a single change of one of the input signals. Happens, when there are multiple paths to the output signal, but each with different delays Question2: Can they occur in two-level SoP circuit? Answer2: Cannot occur in two-level SoP, because all delay levels are the same, namely 2!

Hazard Exercise4 Problem definition: Given function f7() of 4 variables f7( w, x, y, z ) = xy’ + wy + w’x’z, draw its Karnaugh map! Identify, static-1 Hazards Compute consensus terms, and add these terms, so a new f7_free( w, x, y, z ) circuit is hazard free!

Hazard Exercise4 Function f7( w, x, y, z ) = xy’ + wy + w’x’z, with Karnaugh map. Now find hazard locations, by analyzing f7():

Hazard Exercise4 Hazard places are labeled blue (extending to 4 cells in order to minimize terms), yellow (across 4*4 Karnaugh fields), and green These are the products: w’y’z + wx + x’yz f7_free() = xy’ + wy + x’w’z + w’y’z + wx + x’yz will be free of hazards; notice, way more complicated!

Hazard Exercise5 Given the K-Map for function K( a, b, c, d ) below, express K() in as a Boolean function in SoP form Identify where hazards can occur Devise a hazard-free function K_free( a, b, c, d ) that is functionally equivalent to K()

Hazard Exercise5 Boolean function: K( a, b, c, d ) = a’ d + a b c

Hazard Exercise5 Identified hazard locations for K() Marked in blue:

Hazard Exercise5 Added term b c d to K() to form K_free() Consensus term: b c d K_free() = K() + b c d = a’ d + a b c + b c d

Decoders

Students soon design electric circuit in class! Decoders n-to-2n decoder Converts binary code on n=2 input lines to one of 2n=4 output lines When decoder has EN enabled, is referred to as demultiplexer (dmux). EN is often active low. Students soon design electric circuit in class!

Decoders Y0 = I0’ I1’ Y1 = I0 I1’ Y2 = I0’ I1 Y3 = I0 I1 Students design electric circuit for Y0 .. Y3 now: 4 output signals Y0 .. Y3. Use 2-input and-gates, ignore EN

Decoders Converts binary code on n=2 input lines to one of 2n = 4 output lines But EN ignored here! I1 I0 Y0 Y1 Y2 Y3

Decoders with EN Y0 = EN I0’ I1’ Y1 = EN I0 I1’ Y2 = EN I0’ I1

With EN’ signal in circuit, which is EN negated, then: Decoders Map binary code of n input lines to exactly 1 of 2n output lines I1 I0 Y0 Y1 Y2 Y3 EN’ With EN’ signal in circuit, which is EN negated, then: EN’’ = EN

Decoders Sometimes outputs are active low! (EN ignored here) B1B0 F0F1F2F3 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 F0 F1 F2 F3

Decoders Students verify correctness of 5 random active-low cases: B1B0 F0F1F2F3 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 Students verify correctness of 5 random active-low cases: F0 = 0, if B1’ and B0’ F1 = 1, if B1 and B0’ F2 = 1, if B1’ and B0 F3 = 0, if B1 and B0 F3 = 1, if B1’ and B0 F0 F1 F2 F3

Decoders bubble matching is applicable, when for a given logic function F() a differing type of gate is used, different from what F() requires For example, logical and gates are used, yet only nand gates are available, so nands are used instead To keep F() invariant, another negation is inserted in the path of the negated and To be applied to all inputs That is matching a bubble that serendipitously popped up, with another one, to offset its logic inversion

Example: Implement XNOR with DMUX Decoders When using decoders with active low outputs, use bubble matching to use correct gate Example: Implement XNOR with DMUX

Multiplexers

Multiplexers (Data Selectors) Mux S0 selects the function, makes the “direction”: Directs 1 of 2n inputs to single output F = D0 S0’ + D1 S0 S0 F 0 D0 1 D1 Students, build truth table for: S0, D0, D1. Now, in class!

Multiplexers (Data Selectors) Mux Directs 1 of 2n inputs to single output F = D0 S0’ + D1 S0 S0 F 0 D0 1 D1 S0D1D0 F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

Multiplexers Sometimes include Enable input; can be active high or low Effective as universal function generator Students: in class create Truth table for F( EN’, S0, D0, D1 ) Just as decoders were effective as minterm generators (simple functions) and could be used in combination with an OR (NAND) gate to generate functions, a Mux can be used to generate complex functoin

Multiplexers Truth table compacted: EN S0 F 0 0 D0 0 1 D1 1 X 0 Just as decoders were effective as minterm generators (simple functions) and could be used in combination with an OR (NAND) gate to generate functions, a Mux can be used to generate complex functoin

Multiplexers Truth table detailed: Just as decoders were effective as minterm generators (simple functions) and could be used in combination with an OR (NAND) gate to generate functions, a Mux can be used to generate complex functoin

Type 0 Universal Function Implementation with a Mux Uses inputs (X,Y,Z) to “select” function value, by selecting the minterm corresponding to the inputs. If minterm mi is in the function the corresponding Di input is tied to 1 (0 otherwise)

Type 1 Universal Function Implementation with a Mux

A word about “optimization” What are we optimizing? Variables (inputs – connectors) Terms (gates, interconnect) Unique fan-in (IC packages – same number of gates) Number of logic levels (speed) NAND/NOR Implementations (speed, IC packages,…) Complexity (Design time – time to market) Design Time & Flexibility/Cost (FPGA vs. ASIC)