Supplement on Verilog for Algorithm State Machine Chart

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Presentation transcript:

Supplement on Verilog for Algorithm State Machine Chart Based on Fundamentals of Digital Logic with Verilog Design and Fundamental of Logic Design Chung-Ho Chen

Problem: Bit Counter Count the number of 1s’ in A And store the number of 1s in B B = ; while A  do if a 1 then + end if; Right-shift end while;

ASM Chart for Bit Counter Initialize B S2 S1 Start another ? B = ; while A  do if a 1 then + end if; Right-shift end while; s=1, start counting Load B Shift A Update B (a0=1) Conditional output S2 which performs the shift is actually shifted at the next clock edge, so the checking of A, and a0 are performed before the shift of A.

Datapath for the bit counter If n = 8, need how many bits? A shift register A counter register Need to test if a0=1 Need test if A=0? Need load/enable signals +1 +1 A <> 0?

ASM Chart for Bit Counter to Verilog Code module bitcount (Clock, Resetn, LA, s, Data, B, Done); input Clock, Resetn, LA, s; input [7:0] Data; output reg [3:0] B; output reg Done; wire [7:0] A; wire z; reg [1:0] Y, y; reg EA, EB, LB; // control circuit parameter S1 = 2'b00, S2 = 2'b01, S3 = 2'b10; always @(s, y, z) begin: State_table case (y) S1: if (!s) Y = S1; else Y = S2; S2: if (z == 0) Y = S2; else Y = S3; S3: if (s) Y = S3; else Y = S1; default: Y = 2'bxx; endcase end always @(posedge Clock, negedge Resetn) begin: State_flipflops if (Resetn = = 0) y <= S1; else y <= Y; … continued in Part b. ASM Chart for Bit Counter to Verilog Code LB Start another ? y: PS Y: NS s=1, start counting EA Conditional output Z EB

ASM Chart for Bit Counter to Verilog Code always @(y, A[0]) begin: FSM_outputs // Control data path // defaults EA = 0; LB = 0; EB = 0; Done = 0; case (y) S1: LB = 1; S2: begin EA = 1; if (A[0]) EB = 1; else EB = 0; end S3: Done = 1; endcase // datapath circuit // counter B always @(negedge Resetn, posedge Clock) if (!Resetn) B <= 0; else if (LB) else if (EB) B <= B + 1; shiftrne ShiftA (Data, LA, EA, 0, Clock, A); assign z = ~| A; // reduction NOR. endmodule ASM Chart for Bit Counter to Verilog Code Outputs in a state LB Start another ? s=1, start counting EA Conditional output Z EB

Shift Right Register module shiftrne (R, L, E, w, Clock, Q); parameter n = 4; input [n-1:0] R; input L, E, w, Clock; output reg [n-1:0] Q; integer k; always @(posedge Clock) begin if (L) Q <= R; else if (E) Q[n-1] <= w; for (k = n-2; k >= 0; k = k-1) Q[k] <= Q[k+1]; end endmodule