Welcome to the CPLD Training Course Revision 1.1

Course Objectives Learn the basic features of the XC9500 family of CPLDs. Understand the design flow and how the Fitting Report can help users get better performance and utilization from their design. Learn about the Advanced Implementation Options that control the fitting of a design.

Course Agenda XC9500 Architecture CPLD Design Manager Fitting Report and the Timing Analyzer Fitting Report Lab Implementation Options Feedback Options Lab Optimizing for Speed and Density Density Optimization Lab Programming XC9500 Devices

CPLD Training Course XC9500 Architecture

Objectives Learn the basics of the XC9500 architecture Function Block Macrocell Fast Connect Switch Matrix JTAG

Outline Xilinx XC9500 Architecture Summary

Architectural Features High performance 5 ns pin-to-pin logic delays FastCONNECT switch matrix has 100% routability and very high device utilization Flexible function block 36 inputs with 18 outputs Expandable to 90 product terms per macrocell Product term and global three-state enables Product term and global clocks Product term and global set/reset signals 3.3V/5V I/O operation

CPLDs XC9500 devices are similar to having multiple PAL devices interconnected in one chip Best applications Wide functions Fast arithmetic Complex counters Complex state machines PAL/GAL or TTL integration Non-volatile PAL Swi- tch Mat- rix PAL PAL PAL Prog. AND array Fixed OR array FF/ Macro- cell FF/ Macro- cell

Flexible Architecture 3 In-System Programming Controller JTAG Controller JTAG Port I/O Function Block 1 I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O Global Clocks Function Block 3 3 Global Set/Reset 1 Function Block 4 Global Tri-States 2 or 4

Function Block 18 Macrocells per Function Block 18 Macrocell Feedbacks 3 To FastCONNECT From 36 2 or 4 I/O 18 Product- Term Allocators AND Array Global Tri-State Clocks 18 I/O Signals 18 Macrocells per Function Block

Feedback Options . . Function Block I/O Pin Feedback Local Macrocell Feedback To Other Function Blocks Function Block Mux(1) Mcell(1) Pad . . Cross-Point Switch Mux(18) Mcell(18) All Macrocell Outputs Feed Cross-Point Switch Standard Feedback

Three Levels of Feedback Standard - all signals can be routed through the Switch Matrix to eliminate the creation of redundant product terms. (slowest) I/O Pin Feedback - routes output signals to any Function Block, without going through the Switch Matrix. This option gets better performance than Standard feedback, but I/O pins cannot be used for an input signal. (medium) Local Macrocell Feedback - routes the macrocell output into the same Function Block without going through the Switch Matrix. This option gets the fastest performance, but performance is lost if the signal is fed into another Function Block. (fastest)

Macrocell Five product terms are associated with each macrocell Product terms can be used to generate OE, Reset, Set, and Clock Three global clocks and one global set/reset associated with each macrocell D/T-type Register Product terms can be borrowed from other macrocells

Industry’s Best Pin-Locking FastCONNECT Switch Matrix has 100% routability and very high device utilization Product Term Allocator allows any product term to be borrowed by any macrocell in the same function block Footprint compatibility allows for easy migration to larger or smaller devices using the same device package

Product Term Allocator Allocator Architecture lends and borrows product terms to any other macrocell in the same function block. The Allocator only adds an additional 1 ns delay and significantly improves device utilization

Optimized Pin-Locking Not just pin-locking, but flexible placement and fast performance Any of these product terms can be taken from any other macrocell within the same function block. How many product terms is each output using? What is the longest path?

Footprint Compatibility Available Input/ Output Pins XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 44-Pin VQFP 34 44-Pin PLCC 84-Pin PLCC 69 100-Pin TQFP 72 81 100-Pin PQFP 160-Pin PQFP 108 133 34 81 208-Pin HQFP 166 168 352-Pin BGA 166 192 All device types in the same package have the same pinouts. This makes design migration to larger or smaller devices easy and gives the designer more options.

Programming Flexibility Mount XC9500 device to PCB, fixing pinouts Program via download cable (no programmer required) Recompile design, erase & reprogram multiple times Debug logic with extended JTAG test XC9500 advantages Pin-locking architecture maintains pinouts Endurance of 10,000 cycles Extended JTAG test XC9500 ISP Download Cable

Expanded Manufacturing Capability Mount XC9500 and program using standard manufacturing automatic test equipment and JTAG Board test using IEEE 1149.1 compliant JTAG Implement last-minute design changes XC9500 advantages Fast program time (~1 second XC95108) using Automated Test Equipment (ATE) Excellent pin-locking for last-minute design changes Complete IEEE 1149.1 JTAG

Outline Xilinx XC9500 Architecture Summary

Summary First 5V ISP CPLD using Flash technology Designed for ISP Industry’s best pin locking capability Product Term Allocator enables FAST, EFFICIENT, and FLEXIBLE logic generation Footprint Compatibility Full-featured IEEE JTAG Complete, easy-to-use software support

CPLD Training Course CPLD Design Manager

Objectives How to invoke the Design Manager and complete an implementation Features of M1 Design Manager

Outline Design Flow Implementing a Design Checking Results Summary

Design Implementation Design Tools Standard CAE entry and verification tools Xilinx M1 software implements the design The design is optimized for best performance and minimal size Graphical User Interface and Command Line Interface Easy access to other Xilinx programs Manages and tracks design revisions Functional Simulation Design Entry Design Verification Back Annotation Foundation or CAE Schematic, Cores HDL Code Simulation Static Timing Analysis, In-Circuit Testing Design Manager Design Manager Design Implementation

Design Flow for Implementation 1. Invoke Design Manager 2. Start a Project or Open a Project 3. Specify Back Annotation File for Simulation 4. Implement the Design 5. Check Timing Results 6. Download the FPGA/CPLD

Outline Design Flow Implementing a Design Checking Results Summary

Starting the Design Manager Select Programs -> Xilinx Foundation Series -> Design Manager or click on its icon Configurable Flow Engine Controls start/stop points and custom options Timing Analyzer Report on net and path delays JTAG Programmer Creates programming file

Design Manager Project Version Revision Menu bar Project Tool bar Versions Revisions Toolbox Menu bar Tool bar Project Directory containing netlists, also definition of family Version Based on a netlist of the design New version is required when input design is changed Revision An implementation of a Xilinx netlist Multiple revisions typically result from different options or part types

Starting a New Project A. Select File -> New Project B. Specify top level input netlist C. Specify working directory D. Use pull-down menu to specify netlist format.

Setting up a Design for Implementation A. Select Design -> Implement B. Select Part C. Select Options (...see next foil)

Specifying Implementation Options Select Design -> Implement -> Options A UCF contains Timing Specifications associated with the design Enable “Produce Timing Simulation Data” “Produce Configuration Data” enables the creation of a programming file The “Post Layout Timing Report” is useful for estimating performance

Editing Implementation Template To use this form, select Design -> Implement -> Options -> Edit Template Tabs allow custom options to be stored Options enable users to control: device utilization design performance simulator options

Implementing the Design with the Flow Engine Select Design -> Implement -> Run Or press right arrow icon “Run-only” Flow Engine appears The design is implemented and the programming file is created

Outline Design Flow Implementing a Design Checking Results Summary

Report Browser Select Utilities -> Report Browser from the Design Manager Reports are shown once created Double-click to open Yellow sparkles indicates new (not yet read)

Key Report Files Translation Report Fitting Report Reports nets with no source or load Fitting Report Provides detailed information about the fitting of your design Utilization, placement, equations used, pin out, and signal fanout information is provided Post Layout Timing Report Based on block delays and net delays after routing Used for detailed delay analysis after implementation on unconstrained paths

Timing Analyzer Start by clicking on its icon Analyze Timing Specifications after implementation Customize timing reports

Program the CPLD To configure CPLDs, a JTAG file is downloaded CPLDs can be configured In-System, or can be configured using third party programmers More information on programming will be covered later

Outline Design Flow Implementing a Design Checking Results Summary

Summary The Design Manager is a very fast, simple tool to implement a CPLD design The techniques just covered apply to all designs Powerful options for larger and faster designs are discussed in later sections

CPLD Training Course Fitting Report and the Timing Analyzer

Objectives Learn how to use the information contained in the Fitting Report and the reports generated by the Timing Analyzer

Outline Fitting Report Timing Analyzer Summary

Opening the Report Browser Select Utilities -> Report Browser from the Design Manager Reports are shown once created Double-click to open Yellow sparkles indicates new (not yet read)

Resource Summary Design status Resource summary Global net usage

Resources Used Resources sorted by user name Function block resource summary

Product Term Allocation Details Lists product terms being borrowed

Borrowing Product Terms Signal Total Imp Exp Unused Loc Name Pt Pt Pt Pt BANKB0 12 7<- 0 0 FB3_1 (unused) 0 0 /\3 2 FB3_2 (unused) 0 0 \/4 1 FB3_3 CS 13 8<- 0 0 FB3_4 (unused) 0 0 /\4 1 FB3_5 (unused) 0 0 0 5 FB3_6 (unused) 0 0 0 5 FB3_7 (unused) 0 0 0 5 FB3_8 (unused) 0 0 \/5 0 FB3_9 RAS 12 7<- 0 0 FB3_10 TS_REG 1 0 /\2 2 FB3_11 BANKB3 3 0 0 2 FB3_12 MA10_CMD 4 0 0 1 FB3_13 BANKB2 4 0 0 1 FB3_14 BANKB1 4 0 \/1 0 FB3_15 TA_B 6 1<- 0 0 FB3_16 (unused) 0 0 \/5 0 FB3_17 BANKB4 6 5<- \/4 0 FB3_18

Function Block Fan-in Signal fan-in

Implemented Equations Implemented equations in PALASM syntax

Equation Syntax .CLKF Register clock .SETF Register asynchronous set .RSTF Register asynchronous reset .TRST Pin output enable .INTRST Macrocell output enable .PIN Feedback from I/O pin .LFBK Local feedback from macrocell in same function block .PRLD Register preload value NOT AND OR Exclusive OR Combinatorial assignment Registered assignment / * + :+: = := Dot Extensions Logic Operators Definition

Pin Out Final pin assignments generated by the M1 software

Compiler Options List Implementation options selected by the user

Outline Fitting Report Timing Analyzer Summary

Performance Summary Report Design: VSPROM Device: XC9536-7PC44 Program: Timing Report Generator Version XACT-CPLD-v6.0.2a Date: Mon Jan 13 17:10:14 1997 Timing Constraint Summary: TSTPD=FROM:PADS:TO:PADS:7.5 Met TSTCO=FROM:PADS(CLOCK):TO:PADS:6 Met Performance Summary: Pad to Pad (tPD): 7.5ns (1 macrocell level) Pad ‘D0’ to Pad ‘DOUT0’ Clock net ‘CLK’ path delays: Clock Pad to Output Pad (tCO) 5.5ns (1 macrocell level) Clock Pad ‘CLK’ to Output Pad ‘SEL’ (Global Clock) Setup to Clock at the Pad (tSU) 6.5ns (0 macrocell levels) Data signal ‘DONEPIN’ to register ‘ADR0_MC.D’ Clock pad ‘CLK’ Clock to Setup (tCYC) 12.0ns (1 macrocell level) Register ‘S1.Q’ to register ‘ADR0_MC.D’ (Global Clock) Target register drives output net ‘ADR0_MC.Q’ External Timing and Fmax information are in the Performance Summary Report Performance of Timing Constraints can be found by reviewing the TC Report

Performance Report Shows Output Delays 1 2 3 4 5 6 7 7.5 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 \ From \ To ________________________________________________________ Pad to Pad (tPD) (ns) Reports Pad-to-Pad delays (Tpd) C L K 5.5 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 \ Clock \ To _______ Clock Pad to Output Pad (tCO) (ns) Reports Clock Pad-to-Output Pad delays (Tco)

Performance Report Shows Setup Times Setup to Clock at the Pad (tSU) (ns) \ Clock C L K Reports Setup-to-Clock delays (Tsu) \ \ Data \ _______ D0 5.5 D1 5.5 D2 5.5 D3 5.5 D4 5.5 Clock to Setup (tCYC) (ns) (Clock: CLK) A D R _ M C . Q 1 2 3 4 5 6 7 \ From \ \ \ \ Reports Clock-to-Setup delays (Tcyc) \ \ To \ ________________________________________________ ADR0_MC.D ADR1_MC.D ADR2_MC.D ADR3_MC.D ADR4_MC.D ADR5_MC.D ADR6_MC.D ADR7_MC.D 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0

Outline Fitting Report Timing Analyzer Summary

Summary The Fitting Report is a very effective way to understand the fitting of a design in a CPLD Information is provided about the utilization, feedback, and placement in the Fitting Report The Timing Analyzer Design Performance report shows the maximum clock frequency of a design, and the expected input and output delays The Timing Constraints report shows whether or not the timing constraints were met

Lab Quick Quiz (3min) Don’t begin until start called Complete Fitting Report Lab

CPLD Training Course Implementation Options

Objectives Understand the capabilities of each Implementation Option provided by the M1 software Learn when modifying the Implementation Options can help meet performance and utilization expectations

Outline Basic Tab Optimization Tab Advanced Optimization Tab Programming Tab Summary

Options Dialog Box Edit Template command allows the user to modify the Implementation Options Control Files If a Guide file is specified, the pinouts specified will be used If a User Contstraints File is specified, the timing and location constraints will be used Implementation Options Allows user to control logic optimization Controls trade-offs between speed, power, density, and runtime

Basic Tab Use Timing Constraints (Default ON) Perform timing driven optimization using timing constraints in design file or specified .UCF file Use Design Location Constraints (Default OFF) Use macrocell locations and pinouts in design file or specified UCF file. Does not effect guide file pinouts Create Programmable Grounds (Default OFF) Configures all unused I/O pins as ground pins. These pins may be connected to GND or left floating

Basic Tab Default Power Setting (Default STD) Controls default power mode (STD/LOW) for all macrocells in design Overridden by attributes applied to individual signals in design or UCF Default Output Slew Rate (Default FAST) Controls default output slew rate for all outputs in design

Outline Optimization Tab Basic Tab Advanced Optimization Tab Programming Tab Summary

Optimization Tab Timing Optimization (Default ON) General timing optimization tends to speed up slowest paths in design Turning this option off Optimizes for Density and minimizes product terms T-type Register Synthesis (Default ON) Enables conversion of D-type registers to T-type Use Global Resources (Default ON) Enables automatic assignment of clock, output enable and set/reset input signals or pin feedback of I/O signals to global nets Individual signals can be assigned to global nets with attributes

Optimization Tab Use Advanced Fitting (Default ON) Different partitioning algorithm places stronger emphasis on mapping functions that share inputs into the same FB Use if designs become FB input limited Use Local Macrocell Feedback (Default OFF) Logic is mapped into same FB so it can use local feedback rather than Standard Feedback Since Wire-ANDing is done in the Cross-Point Switch, Logic cannot require Wire-ANDing to make the design fit

Optimization Tab Use Local I/O Pin Feedback (Default ON) Allows output functions to feed back through I/O pads rather than using Standard Feedback Can reduce feedback delay by 1 or 2 Ns The M1 Software will use this path only if performance can be improved Note that this option does not apply to XC9536.

Outline Advanced Optimization Tab Basic Tab Optimization Tab Programming Tab Summary

Advanced Optimization Tab Collapsing Product Term Limit (Default 20) Controls the number of product terms that can be borrowed for a single function Collapsing Input Limit (Default 36) Controls the maximum number of signals that can routed to a single function block Default limit is equal to the maximum number of function block inputs in the device

Collapsing Product Term Limit Product Term Allocator D/T Macrocell Product Terms Borrowed Product Terms

Advanced Optimization Tab Multi-level Logic Optimization (Default ON) Controls collapsing of multi-level logic. Multi-level logic is flattened until product term limit is reached.

Outline Programming Tab Basic Tab Optimization Tab Advanced Optimization Tab Programming Tab Summary

Programming Tab Jedec Test Vector File Enables the user to include a Test Vector File (TMV) file in a Jedec programming file. The TMV file is generated when ABEL compiles a design containing user test vectors.

Outline Summary Basic Tab Optimization Tab Advanced Optimization Tab Programming Tab Summary

Summary Changing the default Implementation Options is seldom necessary to fit a design Implementation Options allow customers to improve performance and device utilization The implications of these powerful options and their uses in larger and faster designs will be discussed in the next section

Lab Complete Feedback Options Lab

CPLD Training Course Optimizing for Speed and Density

Objectives Understand the capabilities of the Advanced Optimization Tab in the Implementation Options dialog box Learn good strategies for optimizing designs for speed and density

Outline Parallel and Series Logic Optimizing for Speed Optimizing for Density Examples Optimize Speed and Density Templates Summary

Parallel Logic Macrocell Pterms D/T Parallel Logic Macrocell Pterms Parallel logic occurs when the Fitter maximizes the use of the Product Term Allocator Parallel logic improves the performance of a design by reducing the number of levels of logic required However, this also effectively groups logic together in the same function block Grouping logic can decrease the utilization of any function block Parallel logic usually requires a large number of the function block inputs Borrowed Pterms

Series Logic Feedback Feedback Macrocell Pterms Macrocell Pterms D/T Macrocell Pterms Macrocell Pterms Macrocell Pterms Series logic borrows very few product terms from the Product Term Allocator Series logic is easy to fit inside an XC9500 device because it does not borrow much logic This type of logic does not use very many function block inputs Series logic requires multiple levels of combinatorial logic These pieces are slower than Parallel logic since they use more feedback resources

Parallel vs. Series Product Term Allocator or Feedback? D/T Parallel and Series types of logic can be easily controlled by increasing/decreasing the Collapsing Product Term Limit (CPT) and the Collapsing Input Limit (CI) Increasing the CPT and CI will increase the creation of Parallel logic and should improve the overall performance of a design Decreasing the CPT and CI will force the creation of Series logic and will help improve the device utilization

Advanced Optimization Tab Collapsing Product Term Limit (Default 20) Controls collapsing of multi-level logic. Multi-level logic is flattened until the product term limit is reached. Raising limit can increase speed at expense of density Collapsing Input Limit (Default 36) Controls collapsing of multilevel logic. Multi-level logic is collapsed until input limit is reached Lowering limit can improve density at expense of speed Default limit is equal to the maximum number of function block inputs in the device

Outline Optimizing for Speed Parallel and Series Logic Optimizing for Density Examples Optimize Speed and Density Templates Summary

Timing Constraints Timing Constraints effectively communicate performance expectations to the compiler Use global constraints as a “quick and dirty” way of getting the speed necessary But do not over constrain the design Use signal specific constraints to fine tune the performance Allows software to make informed product term allocation and logic collapsing decisions Assert the Use Timing Constraints option, otherwise constraints will be ignored Constraints permit the optimization of some paths and not others, which gives the tools more flexibility

Increase the Pterm Limit Increase the Product Term Collapsing Limit Increases the flattening of multi-level logic by using product term allocator feature This uses the faster interconnect between product term allocators Raise from 20 (default) to 45 or even 90 (FB pterm limit) Check the Fitting Report to determine the extent to which product terms are being borrowed Assert the Use Timing Optimization option Useful for designs that contain multi-level logic or speed critical signals This option tends to improve slowest paths, whereas constrained paths specify which paths to improve

Feedback Options Use Local Feedback option Use Pin Feedback option Logic mapped into the same FB uses local feedback if Wire-ANDing is not required to make design fit May require placing location constraint on logic Use Pin Feedback option Output functions feedback through I/O pad vs. global feedback, saving 1 to 2 ns

Outline Optimizing for Density Parallel and Series Logic Optimizing for Speed Optimizing for Density Examples Optimize Speed and Density Templates Summary

Reduce the Creation of Parallel Logic Creation of Parallel logic occurs when the Product Term Allocator is used extensively Decrease the Collapsing Pterm Limit to map the logic into smaller chunks Decrease the Collapsing Input Limit to reduce the amount of logic in some function blocks

Use the Advanced Fitting Option This is a different partitioning algorithm that places functions that share inputs into the same function block Use this option if the design becomes function block input limited The Advanced Fitting option will not impact performance This option is on by default

Use the KEEP Attribute 12 Product Term Implementation Use this attribute on high fanout product terms or input intensive nodes Overrides product term and function block input collapsing limits in GUI Boolean logic reduction still performed KEEP 12 Product Term Implementation 6 Product Term Implementation

Global Resources Use global control signals BUFG=OE Using global clock, output enable and set/reset nets saves function block inputs and local product terms Assign high fanout control signals generated in macrocells to global nets FF0 FF5 FF6 FF7 FF8 FF1 FF2 FF3 FF4 BUFG=OE

Outline Examples Parallel and Series Logic Optimizing for Speed Optimizing for Density Examples Optimize Speed and Density Templates Summary

Function Block Input Limited Design ******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT 12 19 STD DPCS 10 19 STD IO 10 14 STD LBE1 10 13 STD SP 10 14 STD **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB1 13 36 39 47 0/0 17 FB2 12 36 37 56 10/0 17 FB3 14 36 36 73 5/1 17 FB4 11 36 38 36 7/0 17 FB5 12 36 40 52 8/1 17 FB6 10 36 38 27 7/0 16 FB7 12 36 35 60 10/1 16 FB8 10 36 37 43 5/3 16 94 363 52/6 133

Solution First, use the Advanced Fitting option **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB1 11 36 41 47 0/0 17 FB2 14 36 43 56 10/0 17 FB3 18 36 37 73 5/1 17 FB4 11 36 41 36 7/0 17 FB5 14 36 36 52 8/1 17 FB6 10 35 37 27 7/0 16 FB7 13 36 39 60 10/1 16 FB8 18 36 36 43 5/3 16 109 363 52/6 133 First, use the Advanced Fitting option If no improvement is seen, gradually reduce the function block input collapse limit to reduce the creation of parallel logic Macrocell count increases when collapse limit decreases

Product Term Limited Design ******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT 12 10 STD DPCS 20 19 STD IO 17 14 STD LBE1 19 13 STD SP 10 14 STD **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB1 13 34 39 74 0/0 17 FB2 12 30 37 87 10/0 17 FB3 14 26 26 73 5/1 17 FB4 11 17 27 75 7/0 17 FB5 12 27 27 84 8/1 17 FB6 10 30 30 84 7/0 16 FB7 12 29 29 83 10/1 16 FB8 10 20 20 83 5/3 16 94 643 52/6 133

Solution Gradually reduce the Product Term Collapse Limit **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB1 11 36 41 28 0/0 17 FB2 14 36 43 45 10/0 17 FB3 18 36 37 46 5/1 17 FB4 11 36 41 47 7/0 17 FB5 14 36 36 54 8/1 17 FB6 10 35 37 46 7/0 16 FB7 13 36 39 45 10/1 16 FB8 18 36 36 78 5/3 16 109 389 52/6 133 Gradually reduce the Product Term Collapse Limit The number of macrocells used will increase

Function Block and Product Term Limited ******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT 12 19 STD DPCS 10 19 STD IO 10 14 STD LBE1 10 13 STD SP 10 14 STD **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB1 13 36 39 74 0/0 17 FB2 12 36 37 87 10/0 17 FB3 14 36 36 73 5/1 17 FB4 11 36 38 75 7/0 17 FB5 12 36 40 84 8/1 17 FB6 10 36 38 84 7/0 16 FB7 12 36 35 83 10/1 16 FB8 10 36 37 83 5/3 16 94 643 52/6 133

Solution First, use the Advanced Fitting option **************** Function Block Resource Summary **************** Function # of FB Inputs Signals Total O/IO IO Block MCells Used Used PT Used Req Avail FB1 11 36 41 28 0/0 17 FB2 14 36 43 45 10/0 17 FB3 18 36 37 46 5/1 17 FB4 11 36 41 47 7/0 17 FB5 14 36 36 54 8/1 17 FB6 10 35 37 46 7/0 16 FB7 13 36 39 45 10/1 16 FB8 18 36 36 78 5/3 16 109 389 52/6 133 First, use the Advanced Fitting option Second, fit the design with Timing Optimization OFF Third, reduce the FB Input Collapse Limit Number of macrocells will increase Finally, reduce the Product Term Collapse Limit

Choosing New Product Term Limit ******** Resources Used by Successfully Mapped Logic ************ Signal Total Signals Loc PWR Slew Pin Name PT Used Mode Rate # Q0 1 8 FB7_5 STD FAST 19 Q1 5 7 FB3_1 STD FAST 35 Q2 3 10 FB6_5 STD FAST 75 Q2 7 3 FB3_1 STD FAST 160 Q4 15 7 FB5_8 STD FAST 100 ******** Resources Required By Unmapped Logic and Pins*********** ** Logic Signal Total Signals Pwr Slew Name PT Used Mode Rate EXIT 8 19 STD DPCS 7 19 STD IO 2 14 STD LBE1 4 13 STD SP 5 14 STD Reduce limits below requirements of largest implemented equations

Outline Optimize Speed and Density Templates Parallel and Series Logic Optimizing for Speed Optimizing for Density Examples Optimize Speed and Density Templates Summary

Speed and Density Templates These Templates enable users to quickly change the Implementation Option settings Optimize Speed Template settings: 20 Pterm Limit 36 Input Limit Macrocell Feedback I/O Pin Feedback Timing Optimization Optimize Density Template settings: 90 Pterm Limit No Timing Optimization

Outline Summary Parallel and Series Logic Optimizing for Speed Optimizing for Density Examples Optimize Speed and Density Templates Summary

Summary Timing Constraints are the most effective way to obtain good performance Raising the Product Term Collapsing Limit increases the creation of Parallel logic, which improves the performance of some designs I/O pin feedback can improve feedback performance significantly for designs that require performance Reducing the Product Term Collapsing Limit will reduce the performance of some modules, but will improve the density Use the KEEP attribute to save product terms on high fanout nets

Lab Density Optimization Lab

CPLD Training Course Programming XC9500 Devices

Objectives Understand the JTAG capabilities of the XC9500 family of devices

Outline Programming Options Summary

Programming Options Optional Targets The “Produce Configuration Data Option” must be asserted for the Fitter to generate a JEDEC file for programming Once the JEDEC file has been created, the JTAG Programmer can be used to download, read back, and verify design configuration data Leaving this option turned off will cause the runtime of the Flow Engine to be shorter

Download Cables There are two cables available for In-System Programming (ISP) The XChecker Cable connects to the serial port of a workstation or PC, and can drive up to 4 - XC9500 devices The Parallel Cable can drive up to 10 XC9500 devices in a JTAG chain, and is at least 5 times faster

JTAG Programmer To start the JTAG Programmer, click on its icon in the Design Manager after Fitting has been completed After the Programmer has been loaded, a workspace will be provided so a JTAG chain of devices can be programmed In this example, a single device system has been setup by default

JTAG Chains One JEDEC file is required for each XC9500 device in the JTAG programming chain To add devices to the JTAG chain, use the command: Edit -> Add Device in the JTAG Programmer window For each remaining device in the chain that is not an XC9500, a Boundary-Scan Description Language (BSDL) file must be specified by the user

JTAG Programmer Operations Program - Downloads the contents of the JEDEC file to the device programming registers Verify - Reads back the contents of the device programming registers and compares them with the JEDEC file Erase - Clears device configuration information Functional Test - Applies user-specified functional vectors from the JEDEC file to the device, compares the results obtained against expected values, and reports any differences to the user Bypass - Ignores this device when addressing devices in the JTAG chain Blank Check - Checks whether a device has been programmed or is erased

Automated Test Equipment Programming Serial Vector Format (SVF) files are used when programming XC9500 devices on ATE The JTAG Programmer allows the creation of (SVF) files for use with ATE systems To create (SVF) files, use the command: OUTPUT -> CREATE SVF FILE...

Outline Programming Options Summary

Summary The XC9500 devices are frequently used in JTAG chains and ATE The Setup of JTAG chains and programming of devices in ATE is easily done with the JTAG Programmer contained in the M1 Design Manager

Lab Complete Programming Lab