The start of a long and hopefully fruitful path CMPE212 First Discussion The start of a long and hopefully fruitful path

TA Information Patrick Sykes Apeksha Lanjile Offices: ITE344, ITE242, and TRC203 Office Hours: W 4:00-5:00PM ITE344 F 12:00-2:00PM ITE242 Contact: psykes1@umbc.edu Apeksha Lanjile Office: ITE340 Office hours: F 12:00PM-2:00PM ITE242 Contact: apeksha2@umbc.edu

Course Website http://userpages.umbc.edu/~psykes1

Course Outline Number Systems Predicate Calculus Binary, Octal, Hexadecimal Predicate Calculus Boolean algebra Combinational Circuits Sequential Circuits Verilog

Introduction to Lab Meet our lab partner Set up Verilog on our gl accounts Play around with the hardware Hopefully finish early

Lab Grading Attendance Completion of the lab If lab isn’t completed on the day given, then it is due before the start of the next lab

Verilog More on this later, we will learn bits and pieces during future labs Verilog is a hardware descriptor language (HDL) that tries to simulate the logic in hardware connectivity It is possible to write code through Xilinx and Quartus software, but they are more suitable for FPGA development

Hardware Power Supply Function Generator Oscilloscope Multimeter Breadboard Integrated Circuits (ICs)

Questions?