Flexible FPGA based platform for variable rate signal generation Raquel Simón Serrano Supervised by: Juan José Vegas Olmos DTU Fotonik, Department of Photonics Engineering Technical University of Denmark, Lyngby, Denmark

Outline Introduction Problem Statement & Proposal solution FPGA & Transceiver architecture Experimental Designs Experimental Results Conclusions & Future work

Digital transmission systems- NRZ encoding 1 0 1 0 1 +V -V 1 0 1 0 1 Transmitter Receiver Transmission medium

How can higher speed transmissions be achieved? More than 2 different electrical levels Encode more than 1 bit per symbol How can higher speed transmissions be achieved? Multilevel codes provide higher efficiency than NRZ codes Multilevel encoding Multilevel signals are generated by combining NRZ signals For communication research NRZ signals are generated by a Pulse Pattern Generator (PPG)

The problem PRESENT FUTURE PPGs are very expensive and bulky devices. Evolution PPG devices FPGA devices PPGs are very expensive and bulky devices.

Why an FPGA? Multiple communication applications The physical connections between logic blocks are programmed by the final user. Multiple communication applications Hardware Description Language

Why the Stratix V FPGA? Stratix V FPGA MP1763B PPG 22.15 cm 2 cm 26.67 cm 45.1 cm 19.05 cm 42.6 cm One transmitter channel and one reverse channel signaling Weight: 33 kg Price: 84,900 $ Seven transceiver channels Weight: 1 kg Price: 4,995 $

Study the quality of the generated signals The objective Program the transceivers embedded in an FPGA to transmit and recieve NRZ signals at the maximum bit rate supported by the device. Study of the FPGA and transceiver architecture Study of the best option to program the transceivers Study the quality of the generated signals Analysis of the results to conclude for which applications the FPGA is useful.

Transceiver architecture PCS Transceiver PMA PMA: Physical Medium Attachment PCS: Physical Coding Sub-layer

Experimental designs FPGA software allows to write HDL code and use predesigned modules. All the transceiver designs were created to transmit at bit rates between 1 Gbps and 12.5 Gbps. One transceiver channel with PRBS 7, 15, 23 or 31 Seven transceiver channels transmitting at the same bit rate with PRBS 7, 15, 23 or 31 Seven transceiver channels transmitting at different bit rate with PRBS 7,15, 23 or 31 One transceiver channel with 40 bit fixed data One transceiver channel adaptable to bit rate changes in real time One transceiver channel with a long fixed pattern within an embedded RAM (Under study)

One transceiver channel with PRBS 7, 15, 23 or 32 Seven transceiver channels transmitting at the same bit rate with PRBS 7, 15, 23 or 32 Seven transceiver channels transmitting at different bit rate with PRBS 7,15, 23 or 32 One transceiver channel with 40 bit fixed data One transceiver channel for dynamic reconfiguration usages One transceiver channel with a long fixed pattern within an embedded RAM

Which modules are needed to program one transceiver channel using Qsys (Method 1)?

Jtag to Avalon Master Bridge Reconfiguration controller Avalon slave Avalon slave Pattern Generator QSYS pattern_out Avalon slave GXB_TXL11 tx_parallel_data tx_serial_data Low Latency PHY IP core Avalon slave rx_serial_data GXB_RXL11 rx_parallel_data Pattern Checker pattern_in reconf Avalon slave Reconfiguration controller out out reconf System clock Reference clock in clkmhz in c100mhz

QSYS Verilog files generated by Qsys cannot be modified Jtag to Avalon Master Bridge Avalon slave Pattern Generator Avalon slave QSYS pattern_out PRBS 7, 15, 23, 31 PRBS 7, 15, 23, 31 Avalon slave tx_parallel_data tx_serial_data Low Latency PHY IP core Avalon slave rx_serial_data rx_parallel_data Pattern Checker pattern_in reconf Avalon slave Reconfiguration controller out out out reconf System clock Reference clock Reference clock in in in Verilog files generated by Qsys cannot be modified

Which modules are needed to program one transceiver channel in Quartus II (Method 2)?

QSYS Quartus II Jtag to Avalon Master Bridge Pattern Generator and checker Slave Interface for Low Latency PHY IP core Slave Interface for Reconfiguration Controller Low Latency PHY IP core Reference clock Reconfiguration controller System clock Connections are programmed manually creating a verilog file

Reconfiguration controller Quartus II Pattern Generator Verilog file can be modified Pattern Checker 40 bit fixed pattern Low Latency PHY IP core Reconfiguration controller

Experimental setup SMA cable

Eye diagram parameters Tbit Eye height Eye width Jitter The best signal performance is achieved when: Jitter is minimum Eye height maximum Eye width maximum

Best case of the experimental results (Seven transceiver channels transmitting at the same bit rate) 2.5 Gbps 7 Gbps 10 Gbps 12.5 Gbps 7 independent channels Bit rate (Gbps) Jitter (ps) Eye width (ps) Eye height (mV) 1 1.98 706.67 439 2.5 1.847 348.89 400 7 2.1 173.33 285 10 2.03 81.51 245 12,5 2.365 56 232

Experimental results One transceiver channel using PRBS 7 with Pre-emphasis (created in Qsys) One channel using a fixed pattern (F0F0F0F0F0) (created in Quartus II) Seven channels transmitting at the same bit rate using PRBS 7 with Pre-emphasis (created in Qsys) Seven channels transmitting at the same bit rate using PRBS 7, capable of transmitting at different bit rates independently with Pre-emphasis (created in Qsys)

RMS Jitter Specifications (ps) Transmitted jitter specifications required by some communication standards Application Data Rate (Gbps) RMS Jitter Specifications (ps) SONET OC-48 2.48832 4.019 Gigabit Ethernet 1.25 13.91 Fibre Channel 1.0625 14.32 XAUI 3.125 8.12 PCI Express 2.5 - 10 3  JITTER (ps) Bit rate (Gbps) Design A Design B Design C Design D 1 2.48 3.08 1.98 2.2 2,5 2.32 2.738 1.847 2.16 7 1.647 2.104 2.1 2.12 10 2.583 4.619 2.03 2.826 12,5 2.878 4.092 2.365 2.992

4-PAM generation experimental set up Attenuator 10 dB NRZ signal 17 dB t delay Combiner Attenuator 10 dB NRZ signal 18 dB

4-PAM experimental results 4-PAM experimental results. NRZ signals provided by seven transceiver channels transmitting at the same bit rate (1 Gbps and 2.5 Gbps) 1 Gbps NRZ signal 2.5 Gbps NRZ signal Bit rate (Gbps) Eye width (ps) Eye height (mV) 1 128.89 181 2.5 271.11 206

4-PAM experimental results 4-PAM experimental results. NRZ signals provided by seven transceiver channels transmitting at the same bit rate (7 Gbps and 10 Gbps) 7 Gbps NRZ signal 10 Gbps NRZ signal Bit rate (Gbps) Eye width (ps) Eye height (mV) 7 92.22 229 10 5.56 35

Conclusions of the designs The transceiver designs created exclusively in Qsys are more simple than the designs created in Quartus II. use predesigned modules instead of HDL codes allows to easily interconnect the different modules Transceiver designs created in Quartus II allows more flexibility than transceiver designs created in Qsys. allows to make modifications to the different modules within a design.

Conclusions of the results Transceiver designs created in Qsys provides better quality transmitted signals than transceiver designs created in Quartus. NRZ signals provided by Stratix V FPGA meet the minimum specifications of various communication standards 4-PAM signals obtained by combining two NRZ signals generated from the transceivers at 1, 2.5 and 7 Gbps result in a sufficiently open eye diagram The replacement of a PPG by an FPGA achieve space and cost saving.

Future work A transceiver design with the possibility to send a long fixed pattern should be performed. A study of the generation of another types of advanced modulation formats (8-PAM, duobinary) should be performed.

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