Status of the DHCAL 1m2 GRPC Acquisition

Slides:

Advertisements

Similar presentations

Julie Prast, DHCAL Meeting, 24 janvier 2008 La carte DIF pour DHCAL (proto au m 2 et au m 3 ) Sebastien Cap, Julie Prast ( LAPP) Christophe Combaret (IPNL)

Advertisements

Contrib passées & à venir du LLR (pour toi, à modifier)‏ VFE DAQ sur EUDET ( ): [C. Jauffret, V. Boudry] test du HardROC.

Micromegas for a DHCAL LAPP, Annecy Catherine Adloff Jan Blaha Sébastien Cap Maximilien Chefdeville Alexandre Dalmaz Cyril Drancourt Ambroise Espagilière.

Second generation Front-end chip for H-Cal SiPM readout : SPIROC DESY Hamburg – le 13 février 2007 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G.

C. Combaret TILC april m2 GRPC Acquisition System C. Combaret, IPN Lyon For the EU DHCAL collaboration

C. CombaretCalice week at UT Arlington, march 2010 SDHCAL status in lyon - Power pulsing, DAQ and m3 C. Combaret, for the IPNL team.

C. Combaret 14 jan 2010 SDHCAL DAQ status in lyon C. Combaret, for the IPNL team.

AHCAL electronics. Status and Outlook Peter Göttlicher for the AHCAL developers CALICE meeting UT Arlington, March 11th, 2010.

08/10/2007Julie Prast, LAPP, Annecy1 The DHCAL DIF and the DIF Task Force Julie Prast, LAPP, Annecy.

EUDET FEE status C. de LA TAILLE. EUDET annual meeting 6 oct 08 cdlt : FEE statrus 2 EUDET module FEE : main issues 2 nd generation ASICs –Self triggering.

RPC detection rate capability ≈ 1/ρ Float-Glass ( Ω-cm) RPC rate capability < Bakelite( Ω-cm) one. New kind of doped glass was developed.

Catherine Adloff16 June 2009 CALICE Technical Board 1 DHCAL-MICROMEGAS Yannis KARYOTAKIS For the LAPP group.

C. Combaret DIF_GDIF_MDIF_D ASU 6x 24 HR2 ASU USB Hub RPi USB2 DCC SDCC RPi USB 1 hub+Rpi for 4 cassettes 1 DCC for 8 cassettes (1 spare) Trigger.

C. Combaret 11/10/ 2008 Status of the DHCAL m2 software C. Combaret IPNL.

Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.

Organization for Micro-Electronics desiGn and Applications HARDROC 3 for SDHCAL OMEGA microelectronics group Ecole Polytechnique CNRS/IN2P3, Palaiseau.

M. Chefdeville LAPP, Annecy, France. Introduction  Motivations for a Digital hadronic calorimeter Count hits instead of measuring energy deposits Reduce.

J. Prast, G. Vouters, Arlington, March 2010 DHCAL DIF Status Julie Prast, Guillaume Vouters 1. Future CCC Use in DHCAL Setup 2. Calice DAQ Firmware Implementation.

Vincent Boudry LLR, École polytechnique CALICE Collaboration meeting U. of Manchester 08/09/2008 Pre-results for the CERN PS tests of the eDHCAL.

1 07/10/07 Forward Vertex Detector Technical Design – Electronics DAQ Readout electronics split into two parts – Near the detector (ROC) – Compresses and.

Towards a 1m 3 Glass RPC HCAL prototype with multi-threshold readout M. Vander Donckt for the CALICE - SDHCAL group.

C. Combaret 27 jan 2010 SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team.

17-19/03/2008 Frédéric DULUCQ Improvements of ROC chips VFE - ROC.

CALICE meeting LYON 2009, Hervé MATHEZ Yannick ZOCCARATO 1 PCB DEVELOPMENTS AT IPNL (PCB and ASIC) PCB for 1m2 of RPC with HR2 William TROMEUR, Hervé MATHEZ,

ASU boards for RPC detectors Production status. Presentation outline Active Sensor Unit electronic board for GRPC detectors – quick reminder – board functional.

European DHCAL development European DHCAL development CIEMAT,IPNL,LAL, LAPP,LLR, PROTVINO, SACLAY CIEMAT,IPNL,LAL, LAPP,LLR, PROTVINO, SACLAY Status :

Julie Prast, Calice Electronics Meeting at LAL, June 2008 Status of the DHCAL DIF Detector InterFace Board Sébastien Cap, Julie Prast, Guillaume Vouters.

14th january 2010 Actual Micromegas USB DAQ ASU and DIF

14 jan 2010 CALICE/EUDET FEE status C. de LA TAILLE.

HARDROC: Readout Chip for CALICE/EUDET Digital Hadronic calorimeter Nathalie Seguin-Moreau.

HaRDROC performance IN2P3/LAL+IPNL+LLR R. GAGLIONE, I. LAKTINEH, H. MATHEZ IN2P3/IPNL LYON M. BOUCHEL, J. FLEURY, C. de LA TAILLE, G. MARTIN-CHASSARD,

Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.

12/09/2007Julie Prast, LAPP, Annecy1 The DIF Task Force and a focus on the DHCAL DIF Remi Cornat, Bart Hommels, Mathias Reinecke, Julie Prast.

June 13rd, 2008 HARDROC2. June 13rd, 2008 European DHCAL meeting, NSM 2 HaRDROC1 architecture Variable gain (6bits) current preamps (50ohm input) One.

CALICE/EUDET FEE status C. de LA TAILLE. 31 aug 2009 EUDET SC meeting Status of JRA3 Front End Electronics 2 ILC front-end ASICs : the ROC chips SPIROC.

News from the 1m 2 GRPC SDHCAL collection of slides from : Ch.Combaret, I.L, H.Mathez, J.Prast, N.Seguin, W.Tromeur, G.Vouters and many others.

SPIROC ADC measurements S. Callier, F. Dulucq, C. de La Taille, M. Faucci, R. Poeschl, L. Raux, J. Rouenne, V. Vandenbussche.

CALICE/EUDET FEE status C. de LA TAILLE. 16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 2 First generation ASICs Readout of physics prototypes (ECAL,

SKIROC status Calice meeting – Kobe – 10/05/2007.

Organization for Micro-Electronics desiGn and Applications Last results on HARDROC 3 OMEGA microelectronics group Ecole Polytechnique CNRS/IN2P3, Palaiseau.

Manqi Ruan Status & plans for gaseous semi-digital HCAL in European.

DHCAL Acquisition with HaRDROC VFE Vincent Boudry LLR – École polytechnique.

Toward a DAQ for the DHCAL m³ (in Test Beams)

HARDROC2: Before production in2p3

HARDROC HAdronic Rpc ReadOut Chip

DIF – LDA Command Interface

ASIC Skiroc 2 Digital part

The European DHCAL status

ASU board: PCB production and testings

Integration of CALICE DAQ in common DAQ

Digital Interface inside ASICs & Improvements for ROC Chips

A proposal to equip the high eta muon stations with High Rate GRPC

Status of the DHCAL DIF Detector InterFace Board

Pre-results for the CERN PS tests of the eDHCAL

CRU Weekly Meeting Discussion on Trigger

Studies on detector and commissioning CALICE Technical meeting

10/month is the present production rate 2 FTE + sporadic contributions

C. de La Taille IN2P3/LAL Orsay

CALICE/EUDET Electronics in 2007

The DHCAL DIF Board For the M2 Prototype

ITS combined test seen from DAQ and ECS F.Carena, J-C.Marin

HARDROC STATUS 6-Dec-18.

HaRDROC status: (Hadronic RPC Detector Read Out Chip for DHCAL)

HaRDROC status: (Hadronic RPC Detector Read Out Chip for DHCAL)

SKIROC status CERN – CALICE/EUDET electronic & DAQ meeting – 22/03/2007 Presented by Julien Fleury.

State of developments on Readout interface of European DHCAL

AIMS 1- Build SDHCAL prototype of 1m3 as close as possible to the one

PID meeting Mechanical implementation Electronics architecture

AIDA KICK OFF MEETING WP9

Presentation transcript:

Status of the DHCAL 1m2 GRPC Acquisition C. Combaret IPNL

Status on march 31st Setup with : Detector : 1m2 GRPC Electronics : 3 IPNL slabs (48 Hardrocs v1), made with 2 single slabs (24 Hardrocs v1 each) 1 DAQ PC (Dell Poweredge 2950) running SL5 1 windows PC for user interface (mostly for convinience and to run Quartus ) XDAQ software running on the DAQ PC

Status on march 31st : Experimental setup Slab #1 DIF #1 Slab #2 DIF #2 Slab #3 DIF #3

Status on march 31st : 48 Hardrocs slabs DIF Slab 1 Slab 2 PCBs conected with 0 ohms resistors (and aluminium tape…)

Status on march 31st : Current data format data format version (8b) timestamp (32b) millitm (32b) global Header (0xB0) DIF ID (8 bits) DIF Trigger counter MSB 24-31 (8 bits) DIF Trigger counter 16-23 (8 bits) DIF Trigger counter 8-16 (8 bits) DIF Trigger counter LSB 0-7 (8 bits) Acq Trigger counter MSB 24-31 (8 bits) Acq Trigger counter 16-23 (8 bits) Acq Trigger counter 8-16 (8 bits) Acq Trigger counter LSB 0-7 (8 bits) Global Trigger counter MSB 24-31 (8 bits) Global Trigger counter 16-23 (8 bits) Global Trigger counter 8-16 (8 bits) Global Trigger counter LSB 0-7 (8 bits) Time DIF MSB 16-23 (8 bits) Time DIF 8-16 (8 bits) Time DIF LSB 0-7 (8 bits) { Beginning of frame : Frame_Header = 0xB4 (8 bits) Hardroc Header : 8 bits BCID : 24 bits (3 bytes) Data : 128 bits (16 bytes) } --> Sent i times according to status of memory of currect Hardroc chip (max = 128) End of frame : Frame_Trailer = 0xA3 } --> Sent j according to number of Hardrocs with data Global trailer (0xA0) CRC MSB CRC LSB Now version 4 Time tag at millisecond Triggers that arrive when DIF is not busy Triggers that arrive when Slab is not busy All Triggers BCID-like counter inside DIF

A run taken one 1slab Data taken for 1 slab with a small PM as cosmic trigger Limitation on 1 slab is due to the fact that we only have small PMs for cosmic trigger

Status on march 31st : where are we? Xdaq Software with Hardroc asics is functional : Stable (tested over few hours) DIF with one 48 Hardroc PCB is fully functional (Slow control, digital readout) 3 DIFs (for 1 m2) used in parallel with Xdaq Calibration package (to record S-curves) is (almost) working

Status on march 31st : What next ? Need a few VHDL lines from Guillaume to synchronize Slabs when a ramfull occurs (Thursday?…) Need to test, test and test before june beam test…