7-5 DRAM ICs High storage capacity Low cost Dominate high-capacity memory application Need “refresh” (main difference between DRAM and SRAM) --dynamic

DRAM cell Fig. 7-12 SRAM: 6 transistors typically DRAM: one transistor and a capacitor => No. of SRAM cells is less than 1/3 of those in DRAM for a given chip size Logic model for the cell Fig. 7-12

DRAM bit slice Fig. 7-13

Block diagram including refresh logic (Fig. 7-14 ) To reduce the no. of pins, the DRAM address is applied serially in two parts with the row address first and the column address second.

Timing for DRAM Write Operation (Fig. 7-15 (a))

Timing for DRAM Read Operation (Fig. 7-15 (b))

7-6 DRAM Types Only SDRAM, DDR SDRAM, RDRAM will be introduced

Synchronous DRAM (SDRAM) Operates with a clock rather than being asynchronous. This permits a tighter interaction between memory and CPU, since the CPU knows exactly when the data will be available. SDRAM also takes advantage of the row value availability and divides memory into distinct banks, permitting overlapped accesses.

Double-data-rate Synchronous DRAM (DDR SDRAM) The same as SDRAM except that data output is provided on both the negative and the positive clock edges.

RAMBUS DRAM (RDRAM) A proprietary technology that provides very high memory access rates using a relatively narrow bus.

7-7 Arrays of Dynamic RAM ICs DRAM controller: handle the requirement for the control and addressing DRAM Performs the following function Controlling separation of the address Provide and signal Performing refreshing operations Providing status signals to the rest of the system