EUDET Elec/DAQ meeting

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Presentation transcript:

EUDET Elec/DAQ meeting Status of the Data Concentrator Card (and other electronics for the DHCAL) Vincent Boudry Franck Gastaldi Antoine Matthieu EUDET Elec/DAQ meeting 12 dec. 2008 DESY

DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008 CERN PS TB November 08 Support is being realized CIEMAT Vincent.Boudry@in2p3.fr DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

The 1 m2 electronics (quick status) Julie Prast & Guillaume Vouters DIF 10-layer board (6 for signals) designed and prototype produced FirmWare & SoftWare operationnal and tested in beam (with 4 HR µMegas card) USB HDMI ASUs RPC: 50×33.3 cm² (24 HR) boards produced μMeGas 32×8 cm² 4 HR produced HR1 ASICs used μMeGas Test board Software Acquisition software based on USB/XDAQ developed “RPC” ASU Ch. Combaret μMeGas + 4 HR ASU + DIF TB data available ⇒ not yet analysed V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

DAQ2 EUDET pour le sDGHCAL DIFs (×120) ASUs DAQ2 PC DCC Clock & Control Digital (Config, Control, Data) Clock & Sync LDA ODR ×10 ⋮×9 Optique GigE Debug USB ×40 : ×14 : Machine clock DCC being developped at LLR 120 DIF → 12 LDA → 4 ODR Gain for DCC ≤ 1600€ 120 DIF → 14 DCC → 2 LDA → 1 ODR V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008 Carte DCC Goals Transparency on the path DIF-LDA Optimization of flux Low cost Pre-proto (proto-0) 4 DIFs connections Implantation et tests du code VHDL Based on a XILINX evaluation board: 128 Mbits SDRAM Daughter board: HDMI connecteurs USB blocs Développements: Marc Kelly (U. Man) : blocs Ser-Des, coding 8b/10b USB blocs (Clément Jauffret) Original VHDL blocs: Mémory controller, commands, buffers (FIFO),…..) V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008 Daughter board DIF Side LVDS Signals (TX & RX) USB part LDA Side MEMORY V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

DCC prototype data flux Modified from Matthias DCC Memory FPGA LDA DIF (×9) V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008 DCC Proto-1 VME 6U VME 6U 16×1 MB ZBT (no latency BUS RAM) Spartan 3 (1500 K gate) Cost est.: 5 protos: ~ 800€/card 20 prods: ~450€/card (Components: ~230€/card) FTDI Est: 1.2A 10mA 400mA 2.25A 30mA V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008 Planning DCC January 09: Finalisation Schematic et routing PCB DCC January- April 09 Fabrication of prototype Test bench mounting Validation & integration of VHDL blocs Mai – June 09 (estimation) Production of boards for the m³ Boucling DCC-DIF / DCC-LDA Connection with the DIF (code on DIF: started) V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008

Test bench & DAQ integration LDA: Components: 1 Proto-DIF ✔, Integration code LDA-DIF on going 1 LDA (✔? fin déc), 1 CCC ✔? 1 ODR + 1 PC DAQ ✔ 1 proto DCC (mars ?) ou proto-0 DAQ Code: DOOCS Mars 09 →Jun 09 Intégration for a m³ Config Database (calib) Slow Control Event Display Raw online analysis CCC: ODR + PC V. Boudry DCC (and other DHCAL electronics) status — DESY, 12 dec. 2008