Impact of NFSI on the clock circuit of a Gigabit Ethernet switch Massiva Zouaoui, Etienne Sicard, Henri Braquet, Ghislain Rudelou, Emmanuel Marsy and Gilles Jacquemod

CONTENTS Context Objectives Methodology Experiments Modeling Approach Conclusion

CONTEXT – HARSH ENVIRONMENT Industrial Electronic Control Harsh environment Temperature, Vibration, Humidity Industrial noise, voltage overstress Systems must be highly robust to Electromagnetic Interference But Increased system performances

Increased performances CONTEXT - SUPPLY DECREASE Less supply, less power dissipation Less noise margin Qualcomm Snapdragon X50 10-nm Increased performances Supply (V) 5.0 0.7 V inside, 1.2V outside 3.3 I/O supply 2.5 Core supply 1.8 1.2 1.0 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n 10n 7n Technology node

Data Rate per pin (Gb/s) CONTEXT - MORE GIGA BITS Multi-Giga-Bit link between processors & memories UHD video, object recognition, 3D capture Less noise margins (reduced voltage swing) Less delay margin (shorter symbols) DDR4: 300 ps 1.0 V swing DDR4x: 250 ps 0.30 V swing 4-PAM 0.15 V swing Data Rate per pin (Gb/s) DDR3: 1.5 ns 1.5 V swing 100 Gb/s Graphics trends GDDR6 GDDR5 Low power trends GDDR4 10 Gb/s LP5 GDDR3 LP4x GDDR2 LP4 LP3 DDR5 DDR trends LP2 DDR4x DDR4 DDR2 DDR3 1 Gb/s 2010 2012 2014 2016 2018 2020

Until now – Post verification OBJECTIVES Until now – Post verification Question: EM field margin ? Sensitive function? Any possibility to predict the EM margin in new products? At Schneider Electrics, a 3-years research project has been setup to investigate immunity simulation of systems Cooperation with Polytech Nice & INSA Toulouse Goal - Prediction

Test-bench Schneider Electrics, radiated immunity CHALLENGES & OPPOORTUNITIES Challenge: Complete system, very difficult to isolate a single device from its environment Little knowledge of the IC Complex susceptibility criteria (loss of function) Opportunities EMC labs Schneider for compliance to standards NEXIO for IC-level measurements Technology analysis form SERMA IBIS models from IC manufacturer CST Studio ™ tool for 3D EM prediction Support for NFSI (A. Boyer, S. Serpaud) IC-EMC software (A. Boyer, E. Sicard) Test-bench Schneider Electrics, radiated immunity

Almost no other choice IMMUNITY MEASUREMENT METHODS IEC standards 47A WG2, WG9 (O. Wada, F. Klotz…) Almost no other choice

NEAR FIELD SCAN IMMUNITY Local No need for specific board Wide band Low cost A. Boyer, “Characterization of the Electromagnetic Susceptibility of Integrated Circuits using a Near Field Scan”, Electronics Letters, 2006

NEAR FIELD SCAN IMMUNITY Pros: Possibility to inject significant perturbation in 3D structures Localized energy to detect weak points Wide band (1 MHz-6 GHz) More than 10 publications Cons: Coupling probe to DUT not very efficient No standardized probe design Test-bench NEXIO, France Probe developed by S. Serpaud, NEXIO

Technology analysis by SERMA EXPERIMENTAL RESULTS 500 MHz 628 MHz 880 MHz GES immunity to Hy, 2mm above the IC, Prototype 1 Technology analysis by SERMA Clock area seems sensitive One IO port seems sensitive Similar results in Hx orientation

MODELING APPROACH DUT input structure model , protection diodes Coupling path model DUT input structure model , protection diodes Passive Decoupling Network Injection model Injection device model Susceptibility criterion model Power limit Voltage threshold Overcurrent RF generator model Behaviour of sensitive & non-linear parts Functionnal model Internal Behavior Perturbation source Extraction of power injection PCB model

GTXCLK Immunity simulation MODELING THE CLOCK-GES LINK Injection probe Radio Frequency Interference VDD VDD PHY Fly over the GES GES Clock Distance to PCB P5_GTXCLK PCB model Sensitive input pin QFP Package model BGA Package model GND GND PHY GTXCLK Immunity simulation

VSS pins NC pins VDD pins 3D RECONSTRUCTION OF THE GES Use GES IBIS information Add some physical parameters Reconstruct 3D view in IC-EMC Near-magnetic field injection probe Package pitch 0.4 mm Package cavity 10 x 10 mm Package height 26 mm Silicon die 8 x 8 mm Bonding wire between the silicon die and package VDD pins VSS pins NC pins

D=0,1 mm D=3 mm PROBE COULING TO PCB Very low efficiency below 50 MHz (<<1%), on a 50-Ω calibration probe Very near field but NOT a d3 law : more or less linear Around 1% coupling at D=1mm, 500 MHz J. Raoult Electromagnetic Coupling Circuit Model of a Magnetic Near-Field Probe to a Microstrip Line, EMC Compo 2015 D=0,1 mm D=3 mm

Freeware tool for simulation of EMC of ICs www.ic-emc.org USE OF IC-EMC IRF NFSI Probe Clock generator PCB GES Freeware tool for simulation of EMC of ICs www.ic-emc.org

Real measured failure Power (dBm) MODELING THE CLOCK Power signal : 100 V range Victim signal: 100 mV range   Criteria Simulated power (dBm) Real measured failure Power (dBm) +/- 200mV 30 33 +/-350mV +/- 1V 41

SYSTEM SIMULATION Built a link between NFSI and far-field illumination What if simulations at system level using CST studio With/without shielding: forecast EM margins

CONCLUSION The immunity of industrial Giga-Bit Ethernet Switch has been analyzed Near-Field Scan in Immunity has been used to identify sensitive zones Comparative immunity measurements were made for 2 versions of IC A modeling approach has been conducted to estimate injected power to failure System EM has been conducted to evaluate margins in different situations A bridge could be made between IC, PCB and system level immunity

MORE ABOUT IC-EMC www.ic-emc.org

Thank you for your attention M. Zouaoui, Study and modelling of electromagnetic susceptibility in complex digital systems, PhD report, 2017, Nice University, France

TEST BOARD DEVELOPPED EMC test boards 10 x 10 cm Main IC isolated on one side Other ICs, IOs, Clocks and Ethernet ports on the other side Easy scan by NFSI Whole control remain complex In case of packet losses, function losses, the whole system must be reset