Computer Architecture: Intro Beginnings, cont. J. Schmalzel S. Mandayam

Course Introduction Overview Content launch: Module 1

Combinatorial Function Blocks Decoders Multiplexers

Real Gates Logic levels are voltage levels Finite current drive Timing diagrams Finite switching speed Propagation delays Noise

Logic Levels are Voltage Levels High Vdd VOHtyp VOHmin VIHmin VILmax VOLmax Low Vss VOLtyp

Finite Current Levels The electrical circuit model for a digital output (or input) includes a series impedance. This helps explain why a gate can’t source/sink unlimited amounts of current (mA v. A). VOH’/VOL’ + RS VOH/VOL

Finite Switching Speeds Example: Switching speed of an inverter. A timing diagram shows behavior as it develops with time. Input (Ideal) Output tr tf

Finite Propagation Delays Example: Switching speed of an inverter. Input (Ideal) Output tPDLH tPDHL

Noise How well logic is able to reject noise is described by its Noise Immunity. The Noise Margin (NM) is the predicted ability of a device to handle noise on its inputs and still reliably determine the correct logic levels. NML = VOLmax - VILmax NMH = VOHmin - VIHmin

Logic Levels/Voltage Levels for 74HC138 w/ VCC=5 Vdc @IOH = -20A High Vdd VOHtyp 4.999 VOHmin 4.9 V (5.0-0.1) VIHmin 3.5 V (0.7*5.0) VILmax 1.5 V (0.3*5.0) VOLmax 0.1 V (0.0+0.1) Low Vss VOLtyp @IOL = +20A 0.001

Variation in VOH and VOL IOH Rs VOH or VOL Ideal VOH or VOL + IOL This is reference direction--that’s why IOH is negative. What is a typical Rs?

Calculation of Rs at IOL of 4 mA IOH Rs VOH or VOL Ideal VOH or VOL + IOL This is reference direction--that’s why IOH is negative. Use 6 Vdc values: 0.26V/.004A = 65 

Propagation delay (6 Vdc) From A, B, or C to any Y output: Max 38 ns From Enable to any Y output: Max 33 ns

Sequential Circuits Include feedback Presence of a clock Behavior is no longer simply a function of the inputs--must be evaluated synchronously with clock Flip-flops D-type J-K type etc.

D-F/F P C Dn Qn+1 1 0 1 X 1 1 1 1 0 X 1 1 0 0 0 X Illegal P D Q CK Q* 1 1 1 1 0 X 1 1 0 0 0 X Illegal P D Q CK Q* Excitation Function: Dn = Qn+1 C

Xilinx F/F’s FDC: D-F/F w/ asynchronous clear FDS: D-F/F w/ synchronous set The FDS will not set upon activation of the set input without also activating clock

State Machines Mealy: Outputs depend on states and on inputs. Moore: Outputs depend only on states. One-Hot: A type of Moore machine in which there is one F/F per state.

Combinatorial Network State Machine Models State Memory Moore Outputs (& One-Hot) Clk Mealy Outputs Inputs Combinatorial Network

Sequential Circuit Design Problem statement State diagram Transition table Simplified excitation functions Implementation Verification

Example Design a sequence detector that will identify 1011. SM 1011 Z

State Diagram Input/Output Input Input/Output Input Moore Mealy Name

One-Hot SMs Moore machines are glitchless since outputs change only synchronously with clock. For relatively small numbers of states, techniques of F/F minimization are largely counterproductive with available “sea-of-gates” FPGA. A 12-state SM: Don’t bother to reduce/encode. A 16-bit counter: Definitely encode states.

SM for 1011 Sequence Detector Reset 1 1 Found None Found1 1 Found4 Z Found2 1 1 Found3 Note: Dashed lines show non-resetting algorithm.

Transition Table Output Present State Input Next State Z F0 F1 F2 F3 F4 X F0’ F1’ F2’ F3’ F4’ 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0

Excitation Functions The Transition Table could be large: 26 = 64, but since this is a One-Hot SM, there can be only one state active at a time. When writing the BA for each excitation function, listing the complemented states is redundant. For example: DF0 = F0•X* + F2•X*, instead of DF0 = F0•F1*•F2*•F3*•F4*•X* + F0*•F1*•F2•F3*•F4*• X* Similarly, DF1 = F0•X + F1•X + F4•X DF2 = F1•X* + F3•X* + F4•X* DF3 = F2•X DF4 = F3•X

Simplification If there are any redundant terms, can simplify; however, for One-Hot approach, there are no simplifications possible since must account for every separate state path.

Implementation Assign one D-F/F per state and complete the combinatorial network required for each input. Implementation of F0 is shown: F0 & + D Q X* P F0 F2 X* Clk The final network output, Z = F4. For reset, use asynchronous F/F inputs: Preset F0 and clear F1-F4.

Verification Check that the SM performs as required. More complex input vectors are required since the internal state memory expands total possible states. Use simulation tools.

The Power of One-Hot Design Can skip transition table--“read” the implementation directly off the state diagram: 1 1 Found None Found1 F0 & + D Q X F1 F1 X C Clk

Sequential Circuit Functions Counters Binary BCD Registers and Latches Shift registers (PIPO, PISO, SIPO, SISO)

Returning to Architecture… The basic model of a computer system: CPU MEM I/O

The Bus-Oriented Architecture CPU I/O MEM Add Data Con

Bus Basics Need to provide a shared medium that prevents contention and which employs methods to grant the use of the bus (arbitration). Bus management methods provide a way to provide bidirectional signal paths. A Y Tri-State: “1” “0” and “High-Z” Open-Collector (Drain): Passively pulled high (“1”) or actively pulled low (“0”) E A E Y 0 1 0 1 1 1 X 0 Z

Questions, Comments, Discussion