Catalog of useful (structural) modules and architectures In this course we will be working mostly at the BEHAVIORAL and STRUCTURAL levels. We will rely on the Altera design tools to do MOST of the physical design and optimization. Here we will quickly review the basic STRUCTURAL building blocks commonly used--complete sets, muxes, demuxes, adders, flip-flops, counters, registers, memory, I/O. We will also briefly review the structure of typical basic computer architectures.

half- adder

full adder full adder full adder

D Q CLK Q’

J Q CLK Q' K

If T = 0, output is unchanged. If T = 1, output “toggles” or T (toggle) flip-flop. If T = 0, output is unchanged. If T = 1, output “toggles” or switches state. Can be implemented with a J-K flip-flop. T Q CLK Q’

Control units. In a computer control unit the "state" of the unit determines what actions will be taken at a given time t. The "state" can be stored, for example, in a set of D flip-flops. If a unit has 2n states, it can be represented in anywhere from n to 2n flip=flops. If we use 2n flip-flops, we call this a "one-hot" representation. Example: basic instruction execution sequence (how many states are required?): Fetch instruction: PC  MAR; MEM(MAR)  MDR; MDR  IR Decode instruction: decide on actions to be taken (e.g., jump, mem fetch / store) Fetch data: immediate operand (in instruction); register operand; memory operand (requires memory access); indirect address (requires 2 memory accesses); … Execute instruction: ALU operation; jump; subroutine call; interrupt; … Store result: immediate operand (in instruction); register operand; memory operand (requires memory access); indirect address (requires 2 memory accesses); …

Basic architectures: finite state machines, stack machines, Turing machines common parallel and distributed models

1. Finite State Machine (FSM) 2. Stack Machine 3. Turing Machine / “Random Access Machine”/ Sequential Computer 4. Multiprocessor Machines

IN Output: may be from each state (“Moore”) or from current state + input (“Mealey”) C A B RESET CLOCK

I/O Popped Item (from “Top”) Control (fsm) Combinational Logic Stack

{Hard Disk, Secondary Devices} (Actual “RAM” Hierarchy) Registers Cache Main Memory (RAM) (Virtual Storage) {Hard Disk, Secondary Devices}

4. Multiprocessor Machines: combinations of the above machines may work together to provide more powerful processing. Examples: Net- Worked or Distri- buted Processors (“MIMD”) (ex. applica- tion: databases) Turing Machine Turing Machine Control ALU+RAM ALU+RAM ALU+RAM ALU+RAM Turing Machine Turing Machine Vector Machine (“SIMD”) (ex. application:differential equations) Turing Machine Turing Machine Turing Machine Turing Machine CPU Sound Typical PC Graphics Printer Pipelined Processors (“MISD”) (ex. application: signal processing)