ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering

STATE REDUCTION

Overview Important to minimize the size of digital circuitry Analysis of state machines leads to a state table (or diagram) In many cases reducing the number of states reduces the number of gates and flops This is not true 100% of the time In this course we attempt state reduction by examining the state table Other, more advanced approaches, possible Reducing the number of states generally reduces complexity.

FSM Optimization State Reduction: Example: Odd parity checker Motivation: lower cost fewer flip-flops in one-hot implementations possibly fewer flip-flops in encoded implementations more don’t cares in next state logic fewer gates in next state logic Simpler to design with extra states then reduce later. Example: Odd parity checker

State Reduction “Row Matching” is based on the state-transition table: If two states have the same output and both transition to the same next state and self-loop or both transition to each other then they are equivalent. Combine the equivalent states into a new renamed state. Repeat until no more states are combined NS output PS x=0 x=1 S0 S0 S1 0 S1 S1 S2 1 S2 S2 S1 0 State Transition Table

FSM Optimization Merge state S2 into S0 Eliminate S2 New state machine shows same I/O behavior Example: Odd parity checker. NS output PS x=0 x=1 S0 S0 S1 0 S1 S1 S0 1 State Transition Table

Row Matching Example State Transition Table NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1 State Transition Table

Row Matching Example NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1 Reduced State Transition Diagram NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1

Partitioning Minimization (Moore) Step 1: P1= (abcdefg) Step 2: P2=(abd)(cefg) Step 3: (abd) 0-successors (bdb) (abd) 1-successors (cfg) (cefg) 0-successors (ffef) (cefg) 1-successors (ecdg) P3: (abd)(ceg)(f) NS output PS x=0 x=1 a b c 1 b d f 1 c f e 0 d b g 1 e f c 0 f e d 0 g f g 0 State Transition Table

Partitioning Minimization Step 3: P3: (abd)(ceg)(f) Step 4: (abd) 0-successors (bdb) (abd) 1-successors (cfg)  b must be removed (ceg) 0-successors (fff) (ceg) 1-successors (ecg) P4: (ad)(b)(ceg)(f) NS output PS x=0 x=1 a b c 1 b d f 1 c f e 0 d b g 1 e f c 0 f e d 0 g f g 0 State Transition Table

Partitioning Minimization Step 4: P4: (ad)(b)(ceg)(f) Step 5: (verify no change) NS output PS x=0 x=1 a b c 1 b a f 1 c f c 0 f c a 0 State Transition Table

STATE ASSIGNMENT

Encoding State Variables Option 1: Binary values 000, 001, 010, 011, 100 … Option 2: Gray code 000, 001, 011, 010, 110 … Option 3: One hot encoding One bit for every state Only one bit is a one at a given time For a 5-state machine 00001, 00010, 00100, 01000, 10000

Summary Important to create smallest possible FSMs This course: use visual inspection method Often possible to reduce logic and flip flops State encoding is important One-hot coding is popular for flip flop intensive designs. credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.