CSE 140 – Discussion 7 Nima Mousavi

Overview Midterm 2 Questions Delay and timing constraints State assignment strategies FSM partitioning Intro to Register Transfer Level (RTL design)

Any questions on Midterm 2?

Delay and Timing Constraints A brief déjà vu moment… TRANSISTORS! Have no fear, we’ll review!

CMOS Transistor as an Imperfect switch! nMOS pMOS 1

How about gates? RC model is used to estimate gate delay Why? Gate speed is determined by how fast it transistions 0  1 1  0 pMOS and nMOS are different! Rp ~ 2Rn Cp ~ Cn ~ Cg What would this cause?

Example Starting with a single inverter: Key ideas: What are different states? What is the resistance and capacitance? What is connected to F? What is this inverter “driving”? Fan out

Now that we are experts.. What does this circuit do? Delay analysis: Try different input combinations

Transistor level delay analysis is difficult! Introducing higher level delay properties for circuits and gates: Contamination delay (Min delay of gate) Minimum time from when an input changes until the output starts to change Propagation delay (Max delay of gate) Maximum time from when an input changes until the output is guaranteed to reach its final value (i.e., stop changing)

Flip Flops Delay in output Q Contamination delay (Min CLK to Q delay): tccq Time after clock edge that Q might be unstable (i.e., starts changing) Propagation delay (Max CLK to Q delay): tpcq Time after clock edge that the output Q is guaranteed to be stable (i.e. stops changing)

Flip Flops – Contd. Constraints for input D Setup time Hold time Time before the clock edge that data must be stable (i.e. not change) Hold time Time after the clock edge that data must be stable

How does this affect our design? - Y U so slow??

Being fast is not favorable either! - Y U so fast??

There is more to this: Clock skew - Y U so variant?? Wires from clock source to different components have different lengths. Resulting in slight variation in clock edges. Side note: How would you solve this problem?

Case 1: R1 is behind In the worst case, R1 receives the latest skewed clock and R2 receives the earliest skewed clock, leaving as little time as possible for data to propagate between the registers.

Case 2: R1 is ahead In the worst case, R1 receives an early skewed clock, CLK1, and R2 receives a late skewed clock, CLK2. The data zips through the register and combinational logic but must not arrive until a hold time after the late clock.

Example

Example

State assignment strategies One hot #states = #bits Wasteful, but easy to implement and debug. Minimum bit transition More bit flips mean more power usage and larger combinational logic. Output based encoding Use output logic to create state encoding.

Example – Min bit transition: 00 01 11 10 S0 S1 1 S4 S3 S2 BAD STATE ASSIGNMENT! Transition Bit flip S0  S1 2 S0  S2 3 S0  S3 S3  S0 S1  S4 S2  S4 S4  S1 Total 17

Example – Min bit transition: 00 01 11 10 S0 1 Transition Bit flip S0  S1 S0  S2 S0  S3 S3  S0 S1  S4 S2  S4 S4  S1 Total

Example – Min bit transition: 00 01 11 10 S0 S1 S3 1 S2 Transition Bit flip S0  S1 1 S0  S2 S0  S3 S3  S0 S1  S4 S2  S4 S4  S1 Total

Example – Min bit transition: 00 01 11 10 S0 S1 S3 1 S2 S4 GOOD STATE ASSIGNMENT! Transition Bit flip S0  S1 1 S0  S2 S0  S3 S3  S0 S1  S4 S2  S4 S4  S1 2 Total 8

State partitioning - Example

State partitioning - Solution

Intro to RTL design Complicated circuits are difficult to implement as FSMs Multi-bit inputs and outputs Complicated functionality Solution: Capture high-level functionality  HLSM (High Level State Machine) Example: Design an HLSM that captures the functionality of an incremental deposit function. Pushing a button adds 10 cents to the account.

Thank you! Any questions?