Using ISE WebPack for the second times

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Presentation transcript:

Using ISE WebPack for the second times Project #2 : The Most Expensive Flip-Flop Embedded and Digital Design PENS-ITS 2014

Gambaran sistem Membuat lampu kedip ‘termahal’ counter n-bit 88 67 Clock 88 67 LED 2Hz 50MHz FPGA

Counter n-bit, berapa-bit ? Input 50MHz  output 2Hz Dibagi 25.000.000 Didekati dengan 2n 225 = 33.554.432 50MHz : 33.554.432 = 1.490116119384765625 Hz 25-bit !!

Alur disain

Nama, letak, dan top-level project Buat project baru, File  New Project

Schematic

Synthesize, implement, generate

Reports

Download and Test Telah sesuai? Jika ya, katakan: berhasil… berhasil… berhasil… hore!!!

Selesai Project #2 : The Most Expensive Flip-Flop Presented by Riset Grup Embedded and Digital Design PENS-ITS 2010