Stefan Ritt Paul Scherrer Institute, Switzerland Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip Stefan Ritt Paul Scherrer Institute, Switzerland

Agenda DRS1 DRS2 DRS3 MEG Experiment searching for me g down to 10-13 Feb. 26th, 2008 Fermilab

Why should we search for m  e g ? Motivation Why should we search for m  e g ?

u c t d s b ne nm nt e m g W Z The Standard Model Generation I II III Fermions (Matter) Quarks u up c charm t top d down s strange b bottom Leptons ne electron neutrino nm muon neutrino nt tau neutrino e electron m muon tau Bosons g photon Force carriers gluon W W boson Z Z boson Higgs* boson Generation I II III *) Yet to be confirmed Feb. 26th, 2008 Fermilab

Today’s goal is to look for physics beyond the standard model The success of the SM The SM has been proven to be extremely successful since 1970’s Simplicity (6 quarks explain >40 mesons and baryons) Explains all interactions in current accelerator particle physics Predicted many particles (most prominent W, Z ) Limitations of the SM Currently contains 19 (+10) free parameters such as particle (neutrino) masses Does not explain cosmological observation such as Dark Matter and Matter/Antimatter Asymmetry Today’s goal is to look for physics beyond the standard model CDF Feb. 26th, 2008 Fermilab

Beyond the SM Find New Physics Beyond the SM High Precision Frontier High Energy Frontier Produce heavy new particles directly Heavy particles need large colliders Complex detectors High Precision Frontier Look for small deviations from SM (g-2)m , CKM unitarity Look for forbidden decays Requires high precision at low energy Feb. 26th, 2008 Fermilab

led to Lepton Flavor Conservation as “accidental” symmetry The Muon Discovery: 1936 in cosmic radiation Mass: 105 MeV/c2 Mean lifetime: 2.2 ms Seth Neddermeyer ne W- e- Carl Anderson ≈ 100% m- nm 0.014 < 10-11 led to Lepton Flavor Conservation as “accidental” symmetry Feb. 26th, 2008 Fermilab

LFV and Neutrino Oscillations Neutrino Oscillations  Neutrino mass  m  e g possible even in the SM g W- m- nm ne e-  LFV in the charged sector is forbidden in the Standard Model n mixing Feb. 26th, 2008 Fermilab

LFV in SUSY While LFV is forbidden in SM, it is possible in SUSY g W- m- nm ne e- g m- e- ≈ 10-12 Current experimental limit: BR(m  e g) < 10-11 Feb. 26th, 2008 Fermilab

History of LFV searches Long history dating back to 1947! Best present limits: 1.2 x 10-11 (MEGA) mTi → eTi < 7 x 10-13 (SINDRUM II) m → eee < 1 x 10-12 (SINDRUM II) MEG Experiment aims at 10-13 Improvements linked to advance in technology cosmic m 10-1 m → e g mA → eA m → eee 10-2 10-3 10-4 10-5 stopped p 10-6 10-7 m beams 10-6 10-9 stopped m 10-10 10-11 SUSY SU(5) BR(m  e g) = 10-13  mTi  eTi = 4x10-16  BR(m  eee) = 6x10-16 10-12 10-13 MEG 10-14 10-15 1940 1950 1960 1970 1980 1990 2000 2010 Feb. 26th, 2008 Fermilab

Current SUSY predictions ft(M)=2.4 m>0 Ml=50GeV 1) current limit MEG goal tan b “Supersymmetric parameterspace accessible by LHC” J. Hisano et al., Phys. Lett. B391 (1997) 341 MEGA collaboration, hep-ex/9905013 W. Buchmueller, DESY, priv. comm. Feb. 26th, 2008 Fermilab

Experimental Method How to detect m  e g ?

Decay topology m  e g m  e g 180º m → e g signal very clean 52.8 MeV m  e g N g m 52.8 MeV 180º 10 20 30 40 50 60 Eg[MeV] e N 52.8 MeV m → e g signal very clean Eg = Ee = 52.8 MeV qge = 180º e and g in time 52.8 MeV 10 20 30 40 50 60 Ee[MeV] Feb. 26th, 2008 Fermilab

“Accidental” Background m  e g Background g g g n m  e nn m m n e Annihilation in flight 180º e m e n m  e nn n m → e g signal very clean Eg = Ee = 52.8 MeV qge = 180º e and g in time Good energy resolution Good spatial resolution Excellent timing resolution Good pile-up rejection Feb. 26th, 2008 Fermilab

Previous Experiments ~ 10-13 Exp./ Lab Author Year DEe/Ee %FWHM DEg /Eg %FWHM Dteg (ns) Dqeg (mrad) Inst. Stop rate (s-1) Duty cycle (%) Result SIN (PSI) A. Van der Schaaf 1977 8.7 9.3 1.4 - (4..6) x 105 100 < 1.0  10-9 TRIUMF P. Depommier 10 6.7 2 x 105 < 3.6  10-9 LANL W.W. Kinnison 1979 8.8 8 1.9 37 2.4 x 105 6.4 < 1.7  10-10 Crystal Box R.D. Bolton 1986 1.3 87 4 x 105 (6..9) < 4.9  10-11 MEGA M.L. Brooks 1999 1.2 4.5 1.6 17 2.5 x 108 (6..7) < 1.2  10-11 MEG ? ~ 10-13 How can we achieve a quantum step in detector technology? Feb. 26th, 2008 Fermilab

~70 People (40 FTEs) from five countries Collaboration ~70 People (40 FTEs) from five countries Feb. 26th, 2008 Fermilab

Paul Scherrer Institute Swiss Light Source Proton Accelerator Feb. 26th, 2008 Fermilab

PSI Proton Accelerator Feb. 26th, 2008 Fermilab

MEG beam line m+ Rm ~ 1.1x108 m+/s at experiment Feb. 26th, 2008 s ~ 10.9 mm m+ Feb. 26th, 2008 Fermilab

Liquid Xenon Calorimeter Calorimeter: Measure g Energy, Position and Time through scintillation light only Liquid Xenon has high Z and homogeneity ~900 l (3t) Xenon with 848 PMTs (quartz window, immersed) Cryogenics required: -120°C … -108° Extremely high purity necessary: 1 ppm H20 absorbs 90% of light Currently largest LXe detector in the world: Lots of pioneering work necessary Liq. Xe H.V. Vacuum for thermal insulation Al Honeycomb window PMT Refrigerator Cooling pipe Signals filler Plastic 1.5m g m Feb. 26th, 2008 Fermilab

Use GEANT to carefully study detector Optimize placement of PMTs according to MC results Feb. 26th, 2008 Fermilab

The complete MEG detector Feb. 26th, 2008 Fermilab

Current resolution estimates Exp./ Lab Author Year DEe/Ee %FWHM DEg /Eg %FWHM Dteg (ns) Dqeg (mrad) Inst. Stop rate (s-1) Duty cycle (%) Result SIN (PSI) A. Van der Schaaf 1977 8.7 9.3 1.4 - (4..6) x 105 100 < 1.0  10-9 TRIUMF P. Depommier 10 6.7 2 x 105 < 3.6  10-9 LANL W.W. Kinnison 1979 8.8 8 1.9 37 2.4 x 105 6.4 < 1.7  10-10 Crystal Box R.D. Bolton 1986 1.3 87 4 x 105 (6..9) < 4.9  10-11 MEGA M.L. Brooks 1999 1.2 4.5 1.6 17 2.5 x 108 (6..7) < 1.2  10-11 MEG 2008 0.8 4.3 0.18 18 3 x 107 ~ 10-13 Feb. 26th, 2008 Fermilab

MEG Current Status R&D http://meg.psi.ch 1999 2000 2001 2002 2003 2004 Goal: Produce “significant” result before LHC R & D phase took longer than anticipated Detector has been completed by the end of 2007 Expected sensitivity in 2008: 2 x 10-12 (current limit: 1 x 10-11) http://meg.psi.ch R&D 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 Engineering Data Taking Set-up Feb. 26th, 2008 Fermilab

Pile-up in the DC system Pile-up can severely degrade the experiment performance ( MEGA Experiment) ! Traditional electronics cannot detect pile-up TDC Need full waveform digitization > 100 MHz to reject pile-up Amplifier Discriminator Measure Time hits Moving average baseline Feb. 26th, 2008 Fermilab

Beam induced background 108 m/s produce 108 e+/s produce 108 g/s Cable ducts for Drift Chamber Feb. 26th, 2008 Fermilab

Pile-up in the LXe calorimeter PMT sum 0.511 MeV meg radiative muon decay 51.5 MeV 50 51 52 E[MeV] t ~100ns (menn)2 + g g’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated g’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed g e m e m Feb. 26th, 2008 Fermilab

Requirements summary Need 500 MHz 12 bit digitization for Drift Chamber system Need 2 GHz 12 bit digitization for Xenon Calorimeter + Timing Counters Need 3000 Channels At affordable price Solution: Develop own “Switched Capacitor Array” Chip Feb. 26th, 2008 Fermilab

The Domino Principle Inverter “Domino” ring chain 0.2-2 ns Inverter “Domino” ring chain IN Waveform stored Out FADC 33 MHz Clock Shift Register “Time stretcher” GHz  MHz Keep Domino wave running in a circular fashion and stop by trigger  Domino Ring Sampler (DRS) Feb. 26th, 2008 Fermilab

Switched Capacitor Array Cons No continuous acquisition No precise timing External (commercial) FADC needed Pros High speed (~5 GHz) high resolution (~12 bit equiv.) High channel density (12 channels on 5x5 mm2) Low power (10 mW / channel) Low cost (< 100$ / channel incl. VME board) Dt Dt Dt Dt Dt Feb. 26th, 2008 Fermilab

Folded Layout Linear inverter chain causes non-linearity Feb. 26th, 2008 Fermilab

“Tail Biting” speed enable 1 2 3 4 1 2 3 4 Feb. 26th, 2008 Fermilab

Sample readout DRS1 Tiny signal I DRS2 Temperature ~kT Dependence DRS3 0.2 pF 20 pF DRS2 I Temperature Dependence ~kT DRS3 Feb. 26th, 2008 Fermilab

DRS3 Fabricated in 0.25 mm 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 12 ch. each 1024 bins, 6 ch. 2048, …, 1 ch. 12288 Sampling speed 10 MHz … 5 GHz Readout speed 33 MHz, multiplexed or in parallel 50 prototypes received in July ‘06 Feb. 26th, 2008 Fermilab

VME Board 32 channels input 40 MHz 12 bit FADC USB adapter board General purpose VPC board built at PSI Feb. 26th, 2008 Fermilab

Bandwidth + Linearity Readout chain shows excellent linearity from 0.1V … 1.1V @ 33 MHz readout Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will be increased significantly with DRS4 0.5 mV max. 450 MHz (-3dB) Feb. 26th, 2008 Fermilab

Signal-to-noise ratio “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) Offset Correction Feb. 26th, 2008 Fermilab

12 bit resolution 11.5 bits effective resolution Feb. 26th, 2008 Fermilab

Sampling speed How far wan we go? 0.250 um technology: 8 GHz Unstabilized jitter: ~70ps / turn Temperature coefficient: 500ps / ºC How far wan we go? 0.250 um technology: 8 GHz 0.130 um technology: 15 GHz ~200 psec PLL Vspeed Reference Clock (1-4 MHz) R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration Feb. 26th, 2008 Fermilab

Timing Reference domino wave 8 inputs shift register Reference clock signal 20 MHz Reference clock 8 inputs PMT hit shift register Reference clock Domino stops after trigger latency MUX Calibrate inter-cell Dt’s for each chip 200 ps uncertainty using PLL 25 ps uncertainty for timing relative to edge Feb. 26th, 2008 Fermilab

What timing can be obtained? Detailed studies by G. Varner1) for LAB3 chip Bin-by-bin calibration using a 500 MHz sine wave Accuracy after calibration: 20 ps 1ns 1) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) Feb. 26th, 2008 Fermilab

On-chip PLL DRS4 Vspeed Simulation: loop filter DRS4 PLL Vspeed Reference Clock fclk = fsamp / 2048 On-chip PLL should show smaller phase jitter If <100ps, no clock calibration required Feb. 26th, 2008 Fermilab

Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS3 Bandwidth (-3db) 300 MHz > 1000 MHz 450 MHz Sampling frequency 1 or 2 GHz 10 MHz … 3.5 GHz 10 MHz … 5 GHz Full scale range ±0.5 V +0.4 …2.1 V +0.1 … 1.1V Effective #bits 12 bit 10 bit Sample points 1 x 2520 9 x 256 12 x 1024 Channel per board 4 N/A 32 Digitization 5 MHz 33 MHz Readout dead time 650 ms 150 ms 3 ms – 370 ms Integral nonlinearity ± 0.1 % ± 0.05% Radiation hard No Yes (chip) Board V1729 (CAEN) - planned (CAEN) Feb. 26th, 2008 Fermilab

What can we learn from acquired waveforms? Waveform Analysis What can we learn from acquired waveforms?

On-line waveform display PMTs “virtual oscilloscope” template fit click pedestal histo Feb. 26th, 2008 Fermilab

QT Algorithm original waveform smoothed and Inspired by H1 Fast Track Trigger (A. Schnöning, Desy & ETH) Difference of Samples (= 1st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time Region for pedestal evaluation integration area smoothed and differentiated (Difference Of Samples) Threshold in DOS Feb. 26th, 2008 Fermilab

Pulse shape discrimination g a Leading edge Decay time AC-coupling Reflections Feb. 26th, 2008 Fermilab

Waveforms can be clearly distinguished t-distribution ta = 21 ns tg = 34 ns Waveforms can be clearly distinguished a g Feb. 26th, 2008 Fermilab

Coherent noise Si Vi (t) All PMTs Pedestal average Charge integration Found some coherent low frequency (~MHz) noise Energy resolution dramatically improved by properly subtracting the sinusoidal background Usage of “dead” channels for baseline estimation Feb. 26th, 2008 Fermilab

Pileup recognition E1 E2 MC simulation DT 8ns DT 50ns original DT 10ns DT 100ns derivative Dt = 15ns E1 E2 DT 15ns MC simulation Rule of thumb: Pileup can be detected if DT ~ rise-time of signals Feb. 26th, 2008 Fermilab

Crosstalk elimination Crosstalk removal by subtracting empty channel subtract Hit Hit Feb. 26th, 2008 Fermilab

Spurious Noise Problem Found “sometimes” a high frequency “ring” on all channels 40 MHz, ~20 mV, 1kHz repetition Finally identified the liquid xenon pump as the source This noise can screw up timing for rare events Without waveform digitizing, this would have been very hard to debug Feb. 26th, 2008 Fermilab

Template Fit Determine “standard” PMT pulse by averaging over many events  “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize c2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values pb Experiment 500 MHz sampling Feb. 26th, 2008 Fermilab

after optimized high pass FIR filter High pass filtering Get rid of baseline (low frequency) noise Improve resolution significantly original waveform template fit integration area after optimized high pass FIR filter Feb. 26th, 2008 Fermilab

Calibrated and linearized signal Baseline Subtraction Baseline Subtraction 100 MHz Clock 12 bit Latch Latch Latch Latch Calibrated and linearized signal Baseline subtracted signal + Latch LUT 12x12 S - S S + - S S Latch Baseline Register <thr Feb. 26th, 2008 Fermilab

Constant Fraction Discr. Delayed signal Inverted signal Sum Clock 12 bit Latch Latch Latch Latch + Latch Latch S + <0 & MULT 0 Feb. 26th, 2008 Fermilab

Data Reduction Zero suppression: hit if max. value > n x s(baseline) Readout window: start / width in respect to trigger Pile-up flag: Zero-crossings of first derivation Re-binning 4:1, 8:1, 16:1 ADC: Numerical integral of hit over baseline TDC: Only simple threshold (usable to recognize accidentals) and time-over-threshold 0.5 ns bins 4 ns bins MEG: Applying to 94% of 100 Hz data Keeping only 6 Hz of waveforms TOT Feb. 26th, 2008 Fermilab

Huffman encoding S 20 16 Diff Bin. Code -1 00 01 1 10 2 11 Huffman 110 01 1 10 2 11 Huffman 110 10 111 Diff Bin. Code 01 1 10 -1 00 Huffman 10 110 1 10 11 110 111 0.6 1 1 0.2 -1 0.4 0.2 2 0.2 S 20 16 Feb. 26th, 2008 Fermilab

Where to perform waveform analysis? Switching from ADC/TDC to ~GHz waveform digitization increases amount of data by ~1000x Many algorithms suitable for on-board (FPGA) processing Charge integration and time estimation (“QT”) Zero-suppression, re-binning, Huffman encoding Basic pile-up recognition (zero-crossings of derivative) Algorithms for embedded CPUs or PC farms Inter-channel cross-talk removal Template fit (floating point) FPGA Front End PC Off-line Analysis DRS Feb. 26th, 2008 Fermilab

DAQ System Principle Drift Chamber Liquid Xenon Calorimeter Timing Counter Active Splitter VME VME LVDS parallel bus Trigger Event number Event type Trigger optical link (SIS3100) Waveform Digitizing Busy Rack PC Rack PC GBit Ethernet Rack PC Rack PC Switch Rack PC Rack PC Rack PC Rack PC Rack PC Event Builder Feb. 26th, 2008 Fermilab

Multi-threading model Calibration Thread Zero-copy ring buffers VME Round-Robin distribution Calibration Thread VME Transfer Thread Collector Thread Calibration Thread Network Calibration Thread Feb. 26th, 2008 Fermilab

Optimal rate with 4 calibration threads Feb. 26th, 2008 Fermilab

2000 channels waveform digitizing DAQ System Use waveform digitization (500 MHz/2 GHz) on all channels Waveform pre-analysis directly in online cluster (zero suppression, calibration) using multi-threading MIDAS DAQ Software Data reduction: 900 MB/s  5 MB/s Data amount: 100 TB/year 2000 channels waveform digitizing DAQ cluster Feb. 26th, 2008 Fermilab

Reduced dead time, integrated triggering Advanced Topics Reduced dead time, integrated triggering

“Residual charge” problem After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses Solution: Clear before write write clear Implemented in DRS4 “Ghost pulse” 2% @ 2 GHz Feb. 26th, 2008 Fermilab

readout shift register ROI readout mode delayed trigger stop normal trigger stop after latency Trigger stop Delay 33 MHz e.g. 100 samples @ 33 MHz  3 us dead time (2.5 ns / sample @ 12 channels) readout shift register Patent pending! Feb. 26th, 2008 Fermilab

Daisy-chaining of channels Domino Wave Generation 1 Channel 0 – 1024 cells 1 1 Channel 1 – 1024 cells 1 Channel 2 – 1024 cells Channel 3 – 1024 cells 1 Channel 4 – 1024 cells Channel 5 – 1024 cells 1 Channel 6 – 1024 cells Channel 7 – 1024 cells DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Feb. 26th, 2008 Fermilab

Interleaved sampling 5 GSPS * 8 = 40 GSPS delays (200ps/8 = 25ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) delays (200ps/8 = 25ps) Feb. 26th, 2008 Fermilab

“Almost” Dead time free system VME board 16 channel CMC1 32 channel MUX CMC2 One board is active while other board is read out Feb. 26th, 2008 Fermilab

DRS4 packaging DRS4 flip-chip DRS4 DRS3 5 mm 9 mm 18 mm Feb. 26th, 2008 Fermilab

New generation of FADCs 8 simultaneous flash ADCs on one chip Require differential input DRS4 has been redesigned with differential output Feb. 26th, 2008 Fermilab

Trigger an DAQ on same board Using a multiplexer, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GHz samples) though same 8-channel FADCs Multiplexer will be included in DRS4 DRS4 global trigger bus trigger FPGA MUX DRS FADC 12 bit 65 MHz analog front end LVDS SRAM No splitter (signal quality!), no dedicated trigger boards, no dedicated scalers Feb. 26th, 2008 Fermilab

“Redefinition of DAQ” Because of the high channel density of the DRS system, it becomes affordable to use waveform digitizing in experiments which today use ADC/TCDs Conventional New AC coupling Baseline subtraction Const. Fract. Discriminator DOS – Zero crossing ADC Numerical Integration TDC Bin interpolation (LUT) Waveform Fitting Scaler (250 MHz) Scaler (50 MHz) Oscilloscope Waveform sampling 400 $ / channel 100 $ / channel DRS ~GHz TDC Disc. ADC Scaler Scope ~100 MHz FADC FPGA CPU Feb. 26th, 2008 Fermilab

Availability DRS4 will become available in larger quantities in summer ’08 Chip can be obtained from PSI on a “non-profit” basis Delivery “as-is” Reference design (schematics) from PSI Costs ~ 10-15$/channel Costs decrease if we find sell more… Full VME board can be purchased from CAEN probably end of ’08 with firmware for peak sensing ADC, QDC, … Struck, others, … ? 32-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz Feb. 26th, 2008 Fermilab

Other experiments using DRS BPM for XFEL@PSI Magic Telescope, Canary Islands 8 chn. with PGA PET scanners MACE Telescope India Feb. 26th, 2008 Fermilab

Conclusions Switched Capacitor Array techniques has prospects to trigger a quantum step in data acquisition The DRS chip has been designed with maximum flexibility and can therefore be used in many applications Collaboration on a scientific basis is very welcome Datasheets, publications: http://midas.psi.ch/drs Feb. 26th, 2008 Fermilab