What Computers Can and Cannot Do Computers deterministically perform instructions No creativity, intuition, etc.

The Fetch/Execute Cycle “Instruction Execution Engine” Fetch/Execute Cycle Fetch next instruction Decode Gather needed data Perform op Save result Repeat

A Five-Step Cycle Ops repeat forever

Anatomy of a Computer All computers have Memory, Control unit, Arithmetic/logic unit (ALU), Input unit, and Output unit

Principal Subsystems of a Computer

1. Memory Memory Code and data Sequence of cells to hold bytes

1. Memory Addresses Values Finite capacity 0 to 232 – 1 (32-bit CPU)

Byte-Size Memory Location Discrete locations are shown as 1B boxes

Byte-Size Memory Location Location can store 8-bits ASCII character Number (how big?) Block of four bytes is word

Random Access Memory Random access memory (RAM) Order and time of access Measured in MB or GB

2. Control Unit Control unit Circuitry handles Fetch/Execute Cycle Typical machine instruction ADD 4000, 2000, 2080

2. Control Unit ADD 4000, 2000, 2080 Sums all three #s? OP Dest, Src1, Src2

Illustration of a single instruction

3. Arithmetic/Logic Unit (ALU) ALU does math Uses logic gates (AND, OR, NOT) +, -, *, /, etc.

4. And 5. Input and Output Units Info => computer Output Info => User Useless without

The Peripherals Peripherals connect to I/O ports Not considered part of computer Encode or decode info b/w computer and physical world

The Peripherals Keyboard Monitor Encodes keystrokes Monitor Decodes memory Peripherals handle physical part of operation

Portable Memory & Hard Drives Storage peripherals can do both I/O USB memory Hard disks/drives

Hard Disk Hard disk stores programs and data Large capacity relative to RAM Slow relative to RAM Programs/data must reside in RAM for use

A Device Driver for Every Peripheral Most peripheral devices are “dumb” Need drivers Video card, monitor Printer Mouse, keyboard

The Program Counter: The PC's PC Program counter (PC) Maintains address of next instr. Instr Fetch (IF) Instr. = MEM[PC] PC = PC + 4

Branch and Jump Instructions Next instr. may not come after previous Instr. may change PC Jump Branch

Instruction Interpretation Process of executing a program is instruction interpretation Our language => computer language

The Fetch/Execute Cycle A five-step cycle: Instruction Fetch (IF) Instruction Decode (ID) Data Fetch (DF) / Operand Fetch (OF) Instruction Execution (EX) Result Return (RR) / Write Result (WR) / Store (ST)

ADD 800, 428, 884

Instruction Fetch (IF) Instr = MEM[PC] PC is 2200 Control Unit (CU) holds instr. Bits of instr are decoded PC updated

IF ADD 800, 428, 884

Instruction Decode (ID) Decoder Determines op to perform Sets up ALU Determines operand addresses Sources Destination Passes to data fetch stage

ID + ADD 800 428 884

Data Fetch (DF) Read data from memory SRC1 = MEM[SRC_ADDR1]

DF 42 12

Instruction Execution (EX) Performs op indicated by ID RES = SRC1 OP SRC2 Result held in ALU

EX 54

Write Result (WR) Writes result to memory MEM[DST_ADDR] = RES Cycle begins again

RR 54