Glen White, SLAC Jan 11 2011 12th ATF2 Project Meeting, KEK Discussion of IPBPM Goals, Status and a Proposal of One Way to Proceed with R&D Glen White, SLAC Jan 11 2011 12th ATF2 Project Meeting, KEK

Overview Required performance for IPBPM system R&D requirements Longer-term, plans to replace IP region with new high-stability and high-precision mover-mounted BPM system What to do in the intermediate timescale? Many R&D items still required that can be addressed with existing system IF can find manpower Some ideas for R&D efforts with existing system Proposal of specific DSP implementation for IPBSM system IPBPM system very important for Goal 1 and Goal 2 of ATF2. Need more effort in this area.

Required Performance for IPBPM System For goal 1 need <10nm RMS vertical jitter at IP for IPBSM max resolution Needs better than 10nm resolution on BPMs Currently shown <5nm with Y.Kim/Honda results First need to measure jitter at IP waist and see how jitter reduces with beamsize- hopefully scales with sigma For goal 2 need <2nm resolution Where to measure? Easiest to move IP waist directly to best performing BPM This best option for goal 2 For goal 1 need IP measurement during IPBSM measurements, need to project IP position to IPBSM waist Increases demands on BPM resolution and stability (gain and offset)

R&D Items Important separate streams of R&D efforts required to meet goals Continued work improving resolution to <2nm Upstream test area For best chances, better pursue both new “low-Q” and continue on from Y.Kim/Honda study? Is there effort available for this? Prove and understand long term stability of high-resolution study and maintainability for non-expert system Need to prove a system that is always available and provides max resolution on multi-minute timescales during IPBSM scans i.e. move from “test” system to “implemented” non-expert system. Non-trivial. Develop “real-time” processing system for use in IP feedback Having stable, low-resolution with offline system (user cuts, data massaging etc by human) very different from automated, fast (~100ns) system which delivers analog signal which is itself high-resolution and stable Need to start putting together a system ASAP to begin R&D for cavity-based IP beam position processor

High-Availability / High-Resolution / Non-Expert Controllable IPBPM Homodyne/heterodyne Need to understand in detail relative performance of both approaches Heterodyne has considerable advantages if it gives good enough performance Fits well into current very well developed and tested cavity BPM processing/analysis/calibration suite of software developed by S. Boogert and team. Homodyne could also be developed into automated system but would need considerable low-level electronics and controls and high-level software work Easiest possible route maybe to develop digital-based heterodyne processing based around existing tools implemented in FPGA logic Leverage all existing high-level tools Tuning / calibration / analysis done using existing high-level tools, FPGA just implements the processing algorithm and provides for data transport to/from FPGA to high-level software (e.g. scale factors, IQ rotation angle, raw waveform data…). FPGA then supplies DAC output for feedback signal for IP FONT system

FPGA IPBPM Processing R&D goals Provision of DSP system ADC + FPGA + DAC + data transfer system Develop processing algorithm in FPGA logic and simulate performance with existing data FPGA implementation of existing heterodyne DDC algorithms plus tuning and calibration implementation Possibility for signal subtraction for overlapping waveforms Math for IP waist position extrapolation Feedback signal formation and output through DAC Implement data transfer hooks and protocols for integration into existing high-level software Implement at ATF2 IPBPM and test performance versus existing offline analysis Optimise latency Assume initial operations for 2-bunch feedback with maximum time between 2 bunches (~300ns) There are tradeoffs between accuracy of position reconstruction and latency in FPGA processing, need to understand these well

FPGA-based IPBPM DSP Solution cPCI “VHS ADC/DAC” with Virtex 4 FPGA from Lyrtech 14-bit 100MHz ADC + DAC (8 channels each) “Model-based toolbox” Simulink interface for FPGA programming and for programming of VHS board Very easy to use, no expert knowledge Currently shipping to SLAC- arrive this month Includes engineering effort from Lyrtech to deliver “low-latency” version of their board.

Architecture High-level Cavity BPM Software BPM ATF-LOCAL Subnet + EPICS High-level Cavity BPM Software VHS-ADC/DAC + FPGA BPM Control Host Running Matlab + Simulink Feedback Electronics

Matlab/Simulink Programming of VHS & FPGA

Matlab/Simulink Programming of VHS & FPGA

Latency Zeroth-order latency of system 100ns Processing blocks will add to this latency Need to investigate latency/accuracy trade-offs Max total latency given by max 2 bunch separation (~300ns) Cable delays + beam propagation delays + analog electronics delay + DSP delay + feedback electronics delay If required, it is possible to work with Lyrtech on latency to further reduce.

IPBPM @ IP Next Steps Current IPBPM processing using SLAC c-band cavity downmix electronics + standard high-level software Resolution ~100nm, min expected ~20nm OK for orbit establishment etc, but not good enough for goals Next step could be to move electronics developed and tested by Y.Kim & Honda-san with demonstrated <5nm resolution to IP region? Also need to move ref cavity’s back to IP region? Then implement online processing system and start with R&D towards high-resolution, high-availability system. Can quickly assemble zeroth-order test to understand performance/latency baseline Continuing, need well-developed R&D plan and dedicated manpower to move R&D forwards Very good PhD student project for example SLAC can provide current system as presented and provide assistance but no resources to fully develop system alone.