Test Boards Design for LTDB Xueye Hu, Hucheng Chen, Joe Mead USTC & BNL 06/20/2012

Outline LTDB Test Boards ADC Mezzanine Card FPGA Carrier Card Test LAr Trigger Digitizer Board ADC Mezzanine Card FPGA Carrier Card Test Conclusion

Outline LTDB Test Boards ADC Mezzanine Card FPGA Carrier Card Test LAr Trigger Digitizer Board ADC Mezzanine Card FPGA Carrier Card Test Conclusion

verify the functionalities LTDB Test Boards LTDB: Phase 1 Upgrade of LAr Front- End electronics Setup irradiation test (Proton beam) LTDB Test boards: Three Steps Step 2 Modular design verify the functionalities 1：ADC Mezzanine Card 2: FPGA Carrier Card Step 1 3: Optical Mezzanine Card (SMU)

Function of FPGA Carrier Card LTDB Digital Mezzanine Card Re-integrate into ¼slice LTDB Digital Mezzanine Card & A LTDB MOTHER Board Step 3 Function of FPGA Carrier Card Function of ADC Mezzanine Card Function of Optical Mezzanine Card LTDB Digital Mezzanine Card Liquid Argon Trigger Digitizer Board MOTHER Board Interface Analog Analog Mezzanine card

Outline LTDB Test Boards ADC Mezzanine Card FPGA Carrier Card Test LAr Trigger Digitizer Board ADC Mezzanine Card FPGA Carrier Card Test Conclusion

... ADC Mezzanine Card Hardware *3 Key Features ADC SMA POWER CONNECTOR POL CONVERTER ADC OSC FMC CONNECTOR ASP-134602-01 ... CLK Driver ADC DRIVER Block Diagram of ADC Test Boards Key Features Input: SMA connectors Output: FMC HPC connector ADC Sampling clock: SMA / OSC/ FPGA differential output ADC reference: internal / external ADC Driver: AD8138 /500krad Clock Driver: CDC1212 /1Mrad Power supply: external supply || on board POL converter

ADC First ADC test board using TI ADS5263 ADS5263: 4-ch, 16bit/14bit, 100MSPS Board has been assembled Second ADC test board using TI ADS5294 ADS5294: 8-ch, 14bit, 80MSPS Third ADC test board using TI ADS5272 ADS5272: 8-ch, 12bit, 65MSPS Survived more than 8Mrad so far Simple architecture and small (6.5 clock cycle) latency PCB design is ongoing

ADC @Test Boards For irradiation test TI ADS5263 Test Board TI ADS5294 Test Board For irradiation test Clearance circle with 3inch diameter

Outline LTDB Test Boards ADC Mezzanine Card FPGA Carrier Card Test LAr Trigger Digitizer Board ADC Mezzanine Card FPGA Carrier Card Test Conclusion

FPGA Carrier Card XILINX Kintex-7 Diff. pairs XC7K325T Single ended FMC CONNECTOR ASP-134602-01 OSCS XILINX Kintex-7 XC7K325T POWER CONNECTOR POL CONVERTER LDO Regulators Diff. pairs Single ended USB USB-UART Bridge Flash DDR3 SO-DIMM 12*10Gbps SMAs SFP ADC DATA GTX DATA Current Monitor JTAG Block Diagram of FPGA Test Board

FPGA Carrier Card Hardware Key Features FMC HPC connectors receive ADC differential data & transmit 10Gbps serial data Memory: DDR3 Ethernet interface: SFP cage & RJ45 RS232 port: Mini-USB & SiLabs CP2103 Configuration: BPI flash & JTAG FPGA: XC7K325T-1FFG900 XADC: monitoring temperature and voltage Power: POL converter LTM4616 LTM4616 & Diode FDLL4148: FPGA power-on sequence Clock: ADC Mezzanine card & differential oscillator SMA: test GTX electrically

FPGA @Test Board For irradiation test Clearance circle with 2.5inch diameter

Outline LTDB Test Boards ADC Mezzanine Card FPGA Carrier Card Test LAr Trigger Digitizer Board ADC Mezzanine Card FPGA Carrier Card Test Conclusion

Setup of Test Preparation Preparation ADC preliminary test Verify ADC functionalities FPGA preliminary test Preparation Make our ADC test boards more generic ML605, KC705, FPGA Carrier card A mapping spreadsheet: Define the FMC HPC connector signals carefully Two FPGA banks transfer differential signals two pairs for clock signals, up to 16 pairs for ADC DATA signals Third FPGA bank for ADC single ended signal

Setup of Test ADC preliminary test ADC Ongoing test FPGA Board ML605 ADS5263 ADS5294 FPGA Carrier card ADC preliminary test ADS5263: power supply, OSC, ADC Driver, Clock Driver work well ADS5294: work well * DCLK, FCLK are not stable with missing cycles It turns out that the analog supply voltage threshold is 1.84V Adjust DC/DC Converters output voltage

Setup of Test Verify ADC functionalities (VHDL code on ML605) ADC interface (S2P) : ADC serial LVDS output parallel data in FPGA Control (SPI): control ADC serial register & configure ADC ChipScope: capture the S2P and SPI data directly from FPGA hardware ADS5263 configuration: 2-wire, 16x serialization, 4 x bit clock, 1 x frame clock, Bytewise mode ADC Sampling clock = 40MHz, FCLK= 40MHz, DCLK= 160MHz Configure ADC and sample ADC data properly ADC Sampling clock = 80MHz, FCLK= 80MHz, DCLK= 320MHz * add clock adjustment module OK ADS5294 configuration: 2-wire, 14x serialization, 4 x bit clock, 1 x frame clock, Wordwise mode SPI works fine & S2P debugging is ongoing

Setup of Test FPGA preliminary test @ power supply works well & power-on sequence has verified with ADM chip and FDLL4148 @ Kintex-7 FPGA is tested with a small LED blinking program JTAG configuration & power on sequence work properly @ MicroBlaze system built on FPGA carried card * DDR3 memory & USB--UART work well Data rate DDR3: 64 bit * 100MHz = 6.4 Gbps ADS5263: 4ch * 16bit * 80MHz = 5.12Gbps ---- DDR3 can handle ADC data input easily * Gigabit Ethernet test is ongoing

Outline LTDB Test Boards ADC Mezzanine Card FPGA Carrier Card Test LAr Trigger Digitizer Board ADC Mezzanine Card FPGA Carrier Card Test Conclusion

Conclusion 1.1: Two ADC (ADS2563, ADS5294) mezzanine cards (Done) 1.2: FPGA carrier card (Done) 1.3: The third ADC (ADS5272) layout (Ongoing) 2.1: ADC (ADS5263) mezzanine card function test (Done) 2.2: ADC (ADS5294) mezzanine card function test (Ongoing) 2.3: ADC Irradiation Test S2P & SPI integrated on ML605 MicroBlaze system (Ongoing)

Thank you !