ECE 3430 – Intro to Microcomputer Systems ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs Lecture #3 Agenda Today MSP432/ARM Programming Model Registers CPU Instructions and Addressing Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Microcontroller MSP432: The 32-bit microcontroller that we will be using in the lab. Based on industry-standard ARM CPU architecture. General Purpose I/O Registers are mapped into memory space and treated as a Registers: normal memory address by the programmer. CPU registers are used to perform general purpose operations (arithmetic, logic). They do not occupy memory space but are accessible by the programmer. There are 13 general-purpose registers in the MSP432 CPU—all of which are 32-bit (R0-R12). Status Register: 32-bit register used mainly for tracking CPU status (PSR). Contains a snapshot of the Z, C, V, and N ALU flags. Stack Pointer: 32-bit register that points to the STACK. The STACK is a first in, last out structure maintained in RAM. The Stack Pointer (SP) points to the top, 32-bit value stored on the stack. Program Counter: 32-bit register that holds the location of the next instruction to be executed by the CPU (PC). Link Register: A 32-bit register commonly used to hold the return address of a subroutine or function (LR). Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Programming Model Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

MSP432 Microcontroller 16-bit reads/writes must use an even address! Memory Addressing: The MSP432 (like most architectures) is a byte-addressable architecture. This means that each address (regardless of precision) references an 8-bit value stored in memory. The MSP432 uses 32-bits for addressing. MSP432 uses a Harvard memory system architecture (distinct address/data bus pairs for program code and data). The MSP432 has 32 address lines = 232 = > 4 billion locations. The CPU reads from/writes to memory by: Providing a 32-bit address to the memory via the address bus (MAB). Accepting/providing an 8,16, or 32-bit data value from/to memory across the data bus (MDB). 16-bit reads/writes must use an even address! 32-bit reads/writes must use a address that is a multiple of 4! Address Data CPU Memory Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Microcontroller Memory Map – A graphical way to illustrate memory. We will use this continually throughout the semester. The MSP432 has an address range from h’00000000’ to h’FFFFFFFF’. Kilobyte -> Kibibyte - KiB = 210 = 1024 Megabyte -> Mebibyte - MiB = KiB2 = 1,048,576 Gigabyte -> Gibibyte - GiB = KiB3 = 1,073,741,824 Ex) When we say “4GB” of memory, that is actually 4,294,967,296= bytes. # of Address Lines - 2(# of address lines) = the number of locations we can access with that many lines. h’00000000’ h’00000001’ : h’FFFFFFFE’ h’FFFFFFFF’ 8-bits Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Instructions and Addressing Instruction: MSP432 instructions are 32 bits long. In addition to which instruction to be executed, the 32-bit instruction code is encoded with information such as source and destination registers, addressing modes, and data size. Opcode: A subset of the instruction code that specifies an instruction in the MSP432 instruction set. Operand: Additional information (parameters) used by an instruction. Operands in the ARM are also typically subsets of the instruction code. Memory Notation: “M” = contents of memory () = address Memory Ex) M(0000h) = 55AAh M(0002h) = FFh Program Counter h’0000’ AAh h’0001’ 55h h’0002’ FFh Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

MSP432 Data Movement Instructions The MSP432 uses load and store operations to accomplish loading from and storing to memory locations. Move instructions are used to initialize CPU registers or move (copy) data from one CPU register to another. All instructions require generating a MAB/MDB read cycle from external memory (to pull in the instruction code). Additional read and/or write cycles are generated by load and store instructions. Loading: Moving data into the CPU. Always generates a read cycle on the MAB/MDB to transfer the payload. Storing: Moving data out of the CPU. Always generates a write cycle on the MAB/MDB to transfer the payload. Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015

MSP432 Load/Store/Move Instructions General Format: <operation> <operands> ; <comment> Data movement (payload not in external memory): MOV <dest>,<src> MOV R2,#100 ; initialize R2 with the value 100 (decimal) MOV R7,R8 ; move (copy) from R8 to R7 Some example load from memory instructions: LDR <dest>,<src> LDR R5, [R6] ; initialize R5 with the 32-bit value at M(R6) LDR R7, [R4,#4] ; initialize R7 with the 32-bit value at M(R4+4) Some example store to memory instructions: STR <src>, <dest> STR R6, [R5] ; store 32-bit value in R6 to M(R5) STR R7, [R8,R4] ; store 32-bit value in R7 to M(R8+R4) STR R8, [R5,#4] ; store 32-bit value in R8 to M(R5+4) LDRH/STRH can be used to specify a 16-bit operation (H = half word). LDRB/STRB can be used to specify an 8-bit operation (B = byte). Lecture #3 ECE 3430 – Intro to Microcomputer Systems Fall 2015