Status on CMOS Sensors: 2005 outcome A. Besson, on behalf of IPHC/IReS Strasbourg DAPNIA Saclay (M8, M15) LPSC Grenoble (ADC) LPC Clermont (ADC) Univ. Frankfurt (M11) Fast integrated signal processing room Temp. Thinning Exploration of fabrication processes Delayed signal processing EUDET SOCLE, Lyon, janvier 2006

Socle, Lyon, janvier 2006Auguste Besson2 Specific aspects of the CMOS VD concept Overall design a priori very similar to TESLA TDR concept (CCD): Basic characteristics: Main R&D effort 5 cylindrical layers R = 15 – 60 mm surface ~ 3000 cm 2 sensor thickness ~ m total number of pixels ~ 300 millions P mean ~ 25 W (full detector; 1/20 duty cycle) operated T > 5 o ? pixels ADC, sparsification support LayerPitcht r.o. N lad N pix P inst diss P mean dis L1 20 m25 s 2025M< 100 W< 5 W L2 25 m50 s 2665M< 130 W< 7 W L3 30 m200 s 2475M< 100 W< 5 W L4 35 m200 s 3270M< 110 W< 6 W L5 40 m200 s 4070M< 125 W< 6 W total142305M< 565 W<29 W concentrated on achieving fast CMOS sensors: signal processing (sparsification) integrated/chip

Socle, Lyon, janvier 2006Auguste Besson3 Status of the main R&D directions Status of the main R&D directions Fast read-out in L1/L2 with // processing of columns –Mimosa 8 (with Saclay) characterized in test beam. –Mimosa 15 (M8 pixel in AMS 0.35 opto) tested in lab. Multi-memory architecture (FAPS) in L3-L5 –Mimosa 12 tested in lab. Radiation hardness (Ionising high TºC –Mimosa 11 characterized in test beam. irradiated with 10 keV X-Rays up to 1 MRad. other on going activities –Fabrication processes –ADC –Thinning –Mimostar-2

// read-out architecture

Socle, Lyon, janvier 2006Auguste Besson5 // read-out architecture: Mimosa 8 Mimosa 8: Test in lab: 55 Fe results –Pixel noise ~ 15 e- –CDS ending each col. Pixel-to-pixel dispersion ~ 8 e- Test beam results (DESY, 5GeV e-) –Analog part Charge ~ 450 e- thin epi layer Typical noise ~ e- S/N (MPV) ~ –Digital part The discriminator works as expected: efficiency / purity / multiplicity Next step: ADC, rad. hardness, AMS 0.35 OPTO, speed - TSMC 0.25 m fab. process with ~ 8 m epitaxial layer - Pixel pitch: 25 m - 3 sub matrices with 3 diode surfaces x 1.2 μm x 1.7 μm x 2.4 μm // columns of 128 pixels with 1 discriminator per column - 8 analogic columns

Socle, Lyon, janvier 2006Auguste Besson6 M8 digital : Efficiency and fake rate Temp. = 20 o C; r.o. = 40 MHz S/N(seed) cut > 5.5 ( discri. threshold =5 mV) Contamination ~< 5 x Fake Hit rate / pixel / event First sensor with integrated signal digitisation ! Architecture to be extended with ADC for EUDET telescope Average hit multiplicity (num of pixels in cluster) Efficiency (%)

Socle, Lyon, janvier 2006Auguste Besson7 Mimosa 15: translation in AMS 0.35 opto TSMC – 0.25 technology < 7 μm epitaxial layer thickness: signal ~ 450 e- while AMS-0.35 opto techno ~< 12 μm thickness: signal ~ e- Translate Mimosa 8 in AMS-0.35 opto techno. First step: Mimosa 15 (fab. in Summer 2005) Pixel with integrated CDS design of Mimosa 8 2 diode sizes: 1.7 x 1.7 μm 2 & 2.4 x 2.4 μm 2 Lab. tests in December-January

Socle, Lyon, janvier 2006Auguste Besson8 Mimosa 15: tests with 55 Fe source 2.4 x 2.4 μm 2 diode: –Gain ~ 50 μV/e - –Q seed ~ 10% of Q tot (instead of ~ 25%) –Q 3x3 ~ 30% of Q tot (instead of ~ 70%) –Noise ~< 10 e- ENC Gain & Noise very close to Mimosa 8 ready for full translation of Mimosa 8 But: less signal charge collected adapt sensing diode size Calibration peak Cluster seed Charge (electrons)Noise (electrons) Mean ~ 8.3 e x 2.4 μm 2 T = 20 o C 25 MHz

Multi-memory architecture

Socle, Lyon, janvier 2006Auguste Besson10 Multi-memory architecture (1) Mimosa 12 (MOSAIC-1) –Layers 3-5. (& layer 2 ?) –Prototype exploring various types & dimensions of memory cells AMS-0.35 m techno 4 capacitors/pixel (35 m pitch) 6 sub-arrays with various MOS capa.: 50, 100, 200 fF Aim for minimal size capacitors providing satisfactory precision, depending on pitch - i.e. layer - (~ 4.6 fF/ m 2 ) Minimal size of capacitor: ~ 50 fF (see also CAP for BELLE) Cap : 100 fF Cap : 200 fF Cap : 50 fF AC : Poly - Poly AC : Nwell - Poly Clamping

Socle, Lyon, janvier 2006Auguste Besson11 Multi-memory architecture (2) 4 capacitors / pixel –Calibration peak with 55 Fe With sampling and read-out With direct read-out Standard pixel Without sampling Standard pixel Without sampling Standard pixel Without sampling 50 fF 100 fF 200 fF t int ~ 230 μs ~ O(1 ms) Storage duration is critical

Radiation hardness

Socle, Lyon, janvier 2006Auguste Besson13 Radiation hardness (1) Mimosa 11: structures –AMS 0.35 μm opto. –8 different sub-matrices Standard rad tol: thin oxyde and guard ring Minimize leakage current Mimosa 11: test beam –DESY, 5 GeV e- –T = 40 o C ; 700 μs (2.5 MHz) –S/N (MPV) ~ 24 –Eff = 99, % N-Well p+ SBSF P-Well P-epi n+ p+ Standard (A0 sub 2) N-Well Partially P+ doped p+ SBSF P+ poly filling P+ poly filling P-Well P-epi n+ p+ Partially P+ doped Rad hard (A3 sub 1)

Socle, Lyon, janvier 2006Auguste Besson14 Mimosa °C10°C40 °C 0kRad 10 keV X-ray Temperature 500kRad (with S. Amar-Youcef, C. Müntz, J. Stroth. Frankfurt) Integration time (ms) Noise (e-) Standard structure Rad hard structure 200 μs Standard structure Rad hard structure 4-pixel cluster: 55 Fe spectrum before (red) and after (green) 1 Mrad of (200 µs integ. time)

Other on-going activities

Socle, Lyon, janvier 2006Auguste Besson16 Other on-going activities Fabrication process exploration –AMS 0.35 μm opto : Excellent performances (M9, M11, M14) Epi. Layer ~ 12 μm S/N ~ (MPV) det ~ % ; sp = m (20 m pitch) Will be used for EUDET – TSMC 0.25 μm Typical cluster charge for MIP ~ 450 e- Epi. Layer ~ 6.5 μm ADC –LPC-Clermont : full flash ADC proto. fab. in Automn 2005 –LPSC-Grenoble : semi-flash ADC proto. subm. in Dec 2005 –IPHC/IReS: Wilkinson double ramp (4.5 bits) –DAPNIA & IReS: Succ. approx. 4 & 5 bits. Thinning (Mimosa-5) –TRACIT company: Thinning at 50 μm successful (mech.) electrical tests foreseen On going tests to thin down to 40 μm

Socle, Lyon, janvier 2006Auguste Besson17 MimoSTAR 2 MimoSTAR-2 –AMS 0.35 μm OPTO. 30 μm pitch –2 matrices 64 x 128, JTAG architecture –Rad. hard structure (based on Mimosa 11) To be installed in STAR (2006) Ionising radiation tolerant pixel validated at temperature up to + 40 o C No active cooling needed at int. time ~< O(1 ms) Prototype of a EUDET telescope demonstrator chip T est-beam results (DESY, 5 GeV e-) 2 r.o. time (2 and 10 MHz) 800 μs and 4 ms (preliminary) Efficiency vs TempS/N (MPV) vs Temp

Socle, Lyon, janvier 2006Auguste Besson18 Summary and Outlook M8: first prototype with discri (TSMC 0.25) Very good m.i.p detection performances implement ADC Signal charge assessed: ~ 450 e - only (AMS 0.35 opto: > 700 e - ) M15: M8 pixel (with CDS) also validated in AMS 0.35 opto M11: rad. tol. room T o up to 1MRad (if t int ~< 1 ms) M12: >~ 50 fF capacitors seem mandatory Not suited to inner most layer but perhaps to 2 nd layer ADC: study of several alternative IReS, LPSC, LPCC, DAPNIA Thinning below 50 μm has started EUDET: Telescope of 5-7 planes of MIMOSA sensors with digital output and integrated zero suppression (M8/M15++) MimoSTAR 2 tested with m.i.p.s demonstrator in 2007

Socle, Lyon, janvier 2006Auguste Besson19 Liste des personnels IPHC/IReS: J.Baudot, A.B., G. Claus, C. Colledani, (G. Deptuch), M. Deveaux, A. Dorokhov, W. Dulinski, M. Goffe, D. Grandjean, F. Guilloux, S. Heini, A. Himmi, Ch. Hu, K. Jaaskelainen, M. Pellicioli, O.Robert, A. Shabetai, M. Szelezniak, I. Valin, M. Winter DAPNIA: M. Besançon, Y. Degerli, N. Fourches, Y. Li, P. Lutz, F. Orsini LPSC: D.Dzahini, M.Dahoumane, H.Ghazlane, J.Y.Hostachy, E.Lagorio, O.Rossetto, D.Tourres LPCC: B.Bohner, R.Cornat, P.Gay, J.Lecoq, L.Royer (Univ. Frankfurt: S. Amar-Youcef)

Socle, Lyon, janvier 2006Auguste Besson20 Mimosa °C10°C40 °C 0kRad 20kRad 10 keV X-ray Temperature 500kRad 1000kRad (with S. Amar-Youcef, C. Müntz, J. Stroth. Frankfurt) Integration time (ms) Noise (e-) Standard structure Rad hard structure 200 μs

Socle, Lyon, janvier 2006Auguste Besson21 M8 digital : Hit multiplicity

Socle, Lyon, janvier 2006Auguste Besson22 Multi-memory architecture (1) Diode « self-bias » Couplage AC 50fF Ampli. Nmos G~10 4 capacités de stockage Ampli. Source Follower Diode « self-bias » Couplage AC 50fF –Poly-Poly –Nwell - Poly Ampli. Pmos G~7 4 capacités de stockage ( Cap =200 fF) Ampli. Source Follower Diode « self- bias » Couplage AC 50fF Ampli. Nmos G~10 2 capacités de stockage « clamping » (CDS intégré) Ampli. Source Follower Cap : 100 fF Cap : 200 fF Cap : 50 fF AC : Poly - Poly AC : Nwell - Poly Clamping