TODAY’S OUTLINE Verilog Codings Concurrent and Sequential If-else Latch Interference Boolean Logic Case Statement Casex Statement

Concurrency and Sequential In verilog coding, there is two important concept called concurrency and sequential Every piece of code that is classed under concurrency is executed at the same time Every piece of code that is classed under sequential is executed one instruction at a time

Cont.. There can be more than one block of concurrency statements module ANDgate (A, B, Y, Z); input A, B; output Y, Z; reg Y; always @ ……. …….. endmodule

Cont.. A sequential statement is for example a statement that starts with “always @ (sensitivity list)” module seq (A, B, Y); input A, B; output Y; reg Y; always @ ( A or B) begin if (A == 1’b1) Y = 1; else if ( A != B) Y = 0; end endmodule

Example module ANDgate (A, B, Y, Z); input A, B; output Y, Z; reg Y, Z; always @ (A or B) begin Y = A & B; end Z = A | B; endmodule module test1 (A, B, C, D, Y); input A, B, C, D; output [2:0] Y; wire [2:0] Y; begin assign Y[0] = D | A; assign Y[1] = B & C; assign Y[2] = ~A ^ (A | C); end endmodule

If – Else Statement If – else statements are sequential statements Used for multiple conditions If – else statement creates logic that depends on priority of the code

Example module if_else (A, B, C, Y, Z); input A, B, C; output Y, Z; reg Y, Z; always @ ( A or B or C) begin if (A & B) Y = 1; Z = B; end else if ( A & C) Y = 0; Z = 1; else Z = 0; endmodule

Incomplete If – Else Statement What happens when a Verilog code with an IF statement but does not have an ELSE but specify all possible combinations What happens when a Verilog code with an IF statement but does not have an ELSE and does not specify all possible combinations

Cont.. When only certain conditions are specified in an IF statement, the synthesis tool assumes that the previous value of a variable is maintained always @ ( A or B) begin if (A == B) Y = 1; else if ( A != B) Y = 0;

Cont.. Based on the Verilog code: If A = B then Y =1 If A != B then Y = 0 For all other values of A and B, the previous value of Y is maintained This is referred to as “latch inference”

Latch Inference If a Verilog code is written using IF statement, w/o all possibilities being specified, a latch is inferred This is undesirable since it would create unnecessary logic usage (redundant latch) A common workaround is to use an ELSE statement

Cont.. The usage of ELSE (for default condition) ensures that no latch will be inferred The other workaround for not inferring latches is to simply specify all the possibilities conditions of A and B

Boolean Logic Verilog coding allows fro Boolean representation of a specific functionality Operation Symbol and & or | not ~ xor ^ Operation Symbol and && or || not !

Cont.. Logical operators return a single bit result Result of logical operations is only either bit 1 (true) or bit 0 (false) Bitwise operators operates on buses and returns the result in bus form

Cont.. Boolean logic is an efficient way to code a functionality Example: A B C Y 1

Cont.. Solution: module boolean (A, B, C, Y); input A, B, C; output Y; wire Y; assign Y = (~A & B) | (A & ~B & C) endmodule Alternatively, IF-ELSE statement can also be used to represent a Boolean logic

Exercise Create a design based on the previous truth table Your design must use if-else statement Make sure your design do not have any latch inference

Answer module exercise (A, B, C, Y); input A, B, C; output Y; reg Y; always @ ( A or B or C) begin if ((~A & B) | (A & ~B & C) ) Y = 1; else Y = 0; end endmodule

Case Statement Case statement is used to represent different options that can be chosen by a set of select signals Its functionality is similar to that of a multiplexer

Cont.. module mux4_case (A,B,C,D,Sel,Y); input A,B,C,D; input [1:0] Sel; output Y; reg Y; always @ (A or B or C or D or Sel) begin case (Sel) 0 : Y = A; 1 : Y = B; 2 : Y = C; 3 : Y = D; default: Y = 1'bx; endcase end endmodule A 1 2 3 B Y C D Sel[1:0]

Cont.. module mux4_case (A,B,C,D,Sel,Y); input A,B,C,D; input [1:0] Sel; output Y; reg Y; always @ (A or B or C or D or Sel) begin case (Sel) 2’b00 : Y = A; 2’b01 : Y = B; endcase end endmodule A 1 2 3 B Y Sel[1:0] If Sel[1:0] = “10” and “11”, Y will maintain its previous value hence latch is inferred

Cont.. module mux4_case (A,B,C,D,Sel,Y); input A,B,C,D; input [1:0] Sel; output Y; reg Y; always @ (A or B or C or D or Sel) begin case (Sel) 2’b00 : Y = A; 2’b01 : Y = B; default: Y = 0; endcase end endmodule A 1 2 3 B Y Sel[1:0]

Case vs If-Else Case statement represents multiplexing conditions If-else statement represents conditional encoding Which one is better to use??

Casex Statement Apart from CASE, there is a separate statement called CASEX Its functionality is similar to that of CASE, but it is for behavioral functionality

Example module mux4_case (A,B,C,D,Sel,Y); input A,B,C,D; input [1:0] Sel; output Y; reg Y; always @ (A or B or C or D or Sel) begin casex (Sel) 2’b00 : Y = A; 2’b01 : Y = B; default: Y = 0; endcase end endmodule A 1 2 3 B Y Sel[1:0]

Next week Lab 2 (Sequential Statements) Be prepared.. Submit ASSIGNMENT 1 on Friday (28 July 2006) That’s all for today. See u on Friday (28 July 2006)