A 2 Gsps Waveform Digitizer ASIC in CMOS 180 nm Technology Jiajun Qin, Lei Zhao, Yiming Lu, Yuxiang Guo, Boyu Cheng, Han Chen, Shubin Liu, Qi An Modern Physics Department, USTC State Key Laboratory of Particle and Electronics, USTC

OUTLINE Overview SCA ASIC Architecture Description Sampling Clock circuit Sampling and Hold Digitization and Readout Performance Measurements AC response New method for Sampling intervals calibration Waveform timing Summary

Overview Waveforms from detectors carry comprehensive and detailed physical information Charge、arriving time、shape etc. Waveform Digitization based on High Speed ADC Power consumption、cost、integration etc. Waveform Digitization based on SCA (switched capacitor array) High sampling speed with slow readout rate Low power、low cost Work in trigger mode Employed in neutrino detection, particle physics, gamma-ray astronomy High precision time measurement In nuclear and particle physics experiments, the waveforms of the pulse signals generated by detectors carry the most comprehensive and detailed physical information. Many experimental physicists in the world have been trying their best to find an effective method to obtain the waveforms of the pulse signals generated by particles. However, the technology of the Analog-to-Digital Converter (ADC) has become a bottle-neck.

Overview Heavy Ion Research Facility in Lanzhou (HIRFL) Precise time measurement for T0 detector: 25 ps RMS Plan one: NINO ASIC + FPGA TDC Plan two: waveform digitization base on SCA Heavy ion research facility in Lanzhou (HIRFL) is the biggest heavy ion experimental facility in China, and the T0 detector, consisting of multiple multi-gap resistive plate chambers (MRPCs), is one of the key components in HIRFL CSR (Cooling Storage Ring) external target experiment. Precise time measurement is required for T0 detector with a time precision of 25 ps MRS, and the current method uses NINO ASIC and FPGA TDC (Time to Digital converter) to get the time information. As an alternative solution, the waveform digitization method based on SCA architecture is proposed. Input operation principle Sampling clock Recovered waveform

OUTLINE Overview SCA ASIC Architecture Description Sampling Clock circuit Sampling and Hold Digitization and Readout Performance Measurements AC response New method for Sampling intervals calibration Waveform timing Summary

Diagram Design Sampling rate: 0.5~2 GHz Resolution: 12-bit Two channels 128 cells/channel Wilkinson ADC in chip Bandwidth: 450 MHz Input Dynamic Range: 1 V

Sampling Clock Circuit Iup Idn Reduce phase offset as much as possible

Sampling and Hold Switch Design Capacitor Design Effect of Cp on bandwidth On-resistance Charge Injection 𝑇 𝑑 =𝑅𝐶 Capacitor Design KTC noise 12-bit resolution A complementary switch is adopted 𝐶>80𝑓𝐹

Digitization and Readout Readout Circuit Diagram Wilkinson ADCs Shared Ramp&Counter Low power Readout shift register ‘token’ 12*5ns*128=7.68us Token

OUTLINE Overview SCA ASIC Architecture Description Sampling Clock circuit Sampling and Hold Digitization and Readout Performance Measurements AC response New method for Sampling intervals calibration Waveform timing Summary

Test System

AC response Scanning DC voltage get DC transfer function Voltage calibration is applied to sampled waveforms Sine wave recorded by SCA is a litter smoother than that of the Oscilloscope (SCA @ 2Gsps, DPO @ 2.5Gsps) Raw DC scans for 128 cells 50 MHz 200 MHz

AC response Input Bus parasitic RC chain 200 MHz sine input Each cell has a rp (~0.3 Ω) and cp (~30 fF), contribute to the amplitude attenuation The amplitude attenuation along the chip input line is verified by the test BW at last cell is about 450 MHz

Sampling Intervals Calibration Where, N is the number of channel cells. Zero-crossing

Sampling Intervals Calibration However, the hypothesis that proportion Vn/tn is a constant value is not always strictly established As shown in AC response, the amplitude reduces along with the input line Slope p at the zero-crossing point decreases along with the input line. So, for left cells for left cells Verified later.

New Time Calibration Method 50.3 MHz sine signal input Time between a and b is equal to one period of input signal are voltage ratio, slightly affected by amplitude attenuation 2000 times:

New Time Calibration Method The roots of the over-determined linear matrix function are the sampling intervals Calculate the periods of 50.3 MHz sine signal with the sampling intervals Red: Classical Time Calibration Blue: New Time Calibration The new correction method is more effective.

Waveform Timing

Summary A 2-channel SCA ASIC was designed and test We come up with a new time calibration method High precision time extraction of waveforms was conducted with this ASIC and the timing resolution is below 20 ps RMS

Acknowledgments Thank Wei Wei in Institute of High Energy, CAS for his constant help in our ASIC design Thank Fukun Tang of Enrico Fermi Institute in University of Chicago for his invaluable guidance in the previous SCA design work We also appreciate the discussion during the previous SCA design work with Wei Wei, Zhi Deng and others

Thank you for your attention!! questions?