AMC13 T1 Rev 2 Preliminary Design Review E. Hazen Boston University 2012-10-30 E. Hazen - AMC13 T1 V2

Scope of this “Review” Background: AMC13 T1 board is being revised to support 10 GbE per request from CDAQ group These boards will be installed during LS1 in HCAL Prefer to keep compatibility with existing T2 For Today: Presentation of schematic-level changes Discussion of open technical issues which may affect T1 Agreement on what needs to be done to proceed with prototyping Not under discussion today: T2 or T3 board design Firmware / Software 2012-10-30 E. Hazen - AMC13 T1 V2

Documentation Please see www.amc13.info (Rev2 link at the top) Schematic and layout preview posted N.B. Not all recent changes are included in the preview documents posted 2012-10-30 E. Hazen - AMC13 T1 V2

CMS MicroTCA Crate 2012-10-30 E. Hazen - AMC13 T1 V2

uTCA Ports Use for CMS Notes: 1. Fabric A (DAQ link) will be operated at 2.5 or 5.0Gb/s in standard AMC13 firmware This link is AC-coupled, CML level 2. Fabric B (TTC) is a non-MGT link operated at 80Mb/s in standard AMC13 firmware This link is DC-coupled, LVDS level 2012-10-30 E. Hazen - AMC13 T1 V2

AMC13 Rev 2 Changes Virtex 6 to Kintex 7 for 10G link support Two-way GbE switch removed, GbE to Spartan chip only (Never used Virtex GbE option) SDRAM size increased from 128MB to 512MB speed to 800MHz DDR (1600MT/s * 32 bits) Clock source changes: Rev 1 used 2x Si570 programmable XO Rev 2 uses Si5338B Quad programmable clock generator TTC Recovered clock to clock-capable input on Kintex 7 Changes to T1-T2 board connector pinout Hope to maintain plug compatibility with existing connector Add 1 pin for additional 12V to be routed to T3 There are two diff pairs unused (GPIO pairs) 2012-10-30 E. Hazen - AMC13 T1 V2

Kintex 7 AMC13 Module – Rev 2 CLK F/O 40.xx CLK To AMCs TTC in SFP CDS TTC in TTS out Kintex 7 SFP IO IO DAQ 10 Gb/s SFP+ GTX GTX GTX GTX Fabric A (DAQ) 12 ports 5.0 Gb/s GTX GTX DAQ 10 Gb/s SFP+ GTX GTX GTX GTX GTX Spare 10 G b/s SFP+ (2) 128Mx16 DDR3 GTX 1600MT/s (6.4 GB/s) Spartan 6 GTP IO Fabric B 80 Mb/s (TTC) DC LVDS GbE GTP MCH1 MMC uC IPMI Front Panel via T3 JTAG LEDs SPI Flash (4x GPIO) 2012-10-30 E. Hazen - AMC13 T1 V2

SDRAM Update Rev 1: (1) MT41J64M16LA 64M x 16 DDR3 Tested at 1600 MT/s (800 MHz) Rev 2: (2) MT41J128M16JT-107 128M x 16 DDR3 Speed rated to 1866 MT/s (933 MHz) Plan to operate at 1600 MT/s (800 MHz) This part promised long-term availability by Micron factory rep 2012-10-30 E. Hazen - AMC13 T1 V2

New clock source 2012-10-30 E. Hazen - AMC13 T1 V2

T1-T2 connectors MMC T2 → T1 SPI Bus Switch, LEDs Propose to add 1-2 pins PWR12V Connector can expand this way only 2.5Gb/s T1 ↔ T2 link GbE to T2 T1 → T2 TTC Data 40MHz clk Spare GPIOs (4) JTAG / Config JTAG / Config 2012-10-30 E. Hazen - AMC13 T1 V2

Clocks: Rev 1 2012-10-30 E. Hazen - AMC13 T1 V2

Clocks: Rev 2 2012-10-30 E. Hazen - AMC13 T1 V2

Design Issue for Discussion... Fabric B is DC driven LVDS by AMC13 (TTC) Possible damage to FPGAs could result if an AMC card is powered down while drivers are active Power up should be OK as drivers come up tri- stated, so it is the power-down case (for hot swap, i.e) at issue This was pointed out by T. Gorsky some time ago. Xilinx claims it is not a problem, but we would like to be conservative... Options: 1. Change to AC-coupling on AMC, redefine protocol 2. Add discrete LVDS buffer on AMC card* 3. Add series i.e. 10 ohm resistors to limit current on AMC card This does not in principle affect the T1 board rev * my preferred solution 2012-10-30 E. Hazen - AMC13 T1 V2

Layout - top 2012-10-30 E. Hazen - AMC13 T1 V2

Layout - Bottom 2012-10-30 E. Hazen - AMC13 T1 V2

Layout Snapshot SFP (TTC) SFP (10Gb) SFP (10Gb) SFP (10Gb) High-speed T1-T2 connector GbE, MGT Link JTAG / Config Two 128Mx16 DDR3 SDRAM SFP (TTC) SFP (10Gb) SFP (10Gb) SFP (10Gb) Low-speed T1-T2 connector (power, MMC signals) XC7K325T-2 FPGA 2012-10-30 E. Hazen - AMC13 T1 V2

Top Components 2012-10-30 E. Hazen - AMC13 T1 V2

Bottom Components 2012-10-30 E. Hazen - AMC13 T1 V2

Other Design Notes MGT clock sources on Kintex-7 TTC 160MHz recovered clock 2 outputs from 5338 Quad clock generator (other two are global logic clock and SDRAM clock) This allows any configuration of link speeds we can conceive of... 2012-10-30 E. Hazen - AMC13 T1 V2

Reserve Slides 2012-10-30 E. Hazen - AMC13 T1 V2

AMC13 Rev 1 Hardware Tongue 3 PCB (4) SFP+ Sites 1 for TTC (160Mb) (optional, for initial programming) (4) SFP+ Sites 1 for TTC (160Mb) 3 for DAQ/etc 6.2Gb Atmel AVR-32 uC MMC Functions Micro USB MMC serial console Tongue 2 PCB Tongue 1 PCB Spartan 6 FPGA Fabric B TTC distribution Firmware management interface to MMC Virtex-6 LX130T FPGA DAQ Functions, buffering 6Gb links to backplane, SFP JTAG Headers MMC programming FPGA programming 2012-10-30 E. Hazen - AMC13 T1 V2