Welcome To Seminar Presentation Seminar Report On Clockless Chips

Contents Abstract Introduction Diamond or Carbon Chip concept Clock concept Problems with synchronous circuits Asynchronous (clockless)circuits How clockless chips works Simplicity in design Asynchronous for higher performance Asynchronous for low noise  Asynchronous for low power  Applications of clockless chips Challenges Conclusion

Introduction Chip:-A small piece of semiconducting material (usually silicon) on which an integrated circuit is embedded. Diamond chip or Carbon chip:-By using carbon or diamond, we can achieve smaller, faster and stronger chips. Clock Chip:-All operations must begin and end according to the clock’s timing (synchronous) signals. Clockless Chip:-Today all faster chip is made by carbon chip uses a technique known as asynchronous logic. It makes hardware fast, power-efficient, less noisy, and easy-to-design.

Diamond or Carbon Chip concept Diamond chip is nothing but carbon chip. Carbon nanotubes were discovered in 1991. The major component using carbon is” Carbon Nanotubes”. It is a nano - size cylinder of carbon atoms are arranged in hexagonal pattern. Carbon transistors are made of graphene.

Clock concept The clock is a tiny crystal oscillator that resides in the heart of every  microprocessor chip. All components operate exactly once per clock tick and their outputs need to be ready and next clock tick. One advantage of a clock is that, the clock signals to the devices of the chip when to input or output.

Problems with Synchronous Circuits Low performance:-All the components are tied up together and the system is working on its worst case execution. Low speed:-A traditional CPU cannot "go faster" than the expected worst-case performance of the slowest instruction. High power dissipation:-Clock is a tiny crystal oscillator that keeps vibrating during all time as long as the system is power on, this lead into high power dissipation by the synchronous circuit. High electro-magnetic noise:-It is associated with electromagnetic waves that produce electromagnetic noise due to oscillations.

Asynchronous(clockless) circuits(1) It uses handshakes signals for communication to each other components. In this case the circuits are not tied up together and forced to follow the global clock timing signals . Each and every component is loosely and they run at average speed. 

Asynchronous(clockless) circuits(2) Asynchronous is can be achieved by implementing three vital techniques: Clock less chips implementation: In order to achieve asynchronous as final goal one must implement the electronic circuits without using central clock. Throwing away global clock: By throwing away the global clock it is possible now for components to be completely not synchronized. Standardize of components: There is average speed in which the design of system is dedicated to compile and the worst case execution will be avoided. 

How clockless chips works Clocked chips represent ones and zeroes using low and high voltages on a single wire circuits. Clockeless chips use two wires, giving the chip communications pathways, not only to send bits, but also to send "handshake" signals to indicate when work has been completed.

Simplicity in design There in no complexity of a simple design for clock less chips. Integrated pipeline mode plays an important role in total system design. There are about four factors regarding pipeline : Domino logic  Delay insensitive Bundle data  Dual rail

Domino logic Domino logic is a CMOS(Complementary MOS)-based which were based on either PMOS(Positive MOS) or NMOS(Negative MOS) transistors. In a cascade structure consisting of several stages, the structure is hence called Domino CMOS Logic. They have smaller areas than conventional CMOS logic.  Higher operating speeds are possible.

Delay insensitive Delay insensitive circuit is a type of asynchronous circuit which performs a logic operation often within a computing processor chip. The sequencing of computation in delay insensitive circuit is determined by the data flow. Handshake signals are used to indicate the readiness of such a circuit to accept new and the delivery of such data by the requesting function. In a delay insensitive circuit, there is no need to provide a clock signal to determine a starting time for a computation.

Dual rail Dual rail is the technique employed to influence asynchronization of circuits by establishing two connections to any circuit that is in connection. Hence it provides one line for handshakes signals and the other for data transmission.

Bundled-data Bundled-data pipelines include novel data-dependent delay  lines with integrated control circuitry to efficiently implement speculative completion sensing. Simplifies the design of such nonlinear pipelines.

Asynchronous for higher performance In order to increase the performance of the circuit, the following are basics to be implements. Data-dependent delays. All carry bits need to be computed. 

Asynchronous for low noise Any system with clock will be having oscillations in it and will create electromagnetic noise. This problem is greatly reduced to significant considerable range by discarding the central clock and the spectra radiation are much smoother in asynchronous circuits.

Asynchronous for low power Power consumption is very important aspect in designing any mobile and to increase the battery capacity and life for battery driven devices. Hence asynchronization of power is completely inevitable to achieve a low level of power dissipated. The circuit should consume power only when and where active.

Applications of clockless chips Wearable computers: Wearable computers are mobile computers that are worn on the body. These are especially useful for applications that require computational support. Infrared communication: Infrared communication has asynchronous in nature then clockless chips are implemented for its design. In pagers (beeper):.A one-way numeric ,alphanumeric pagers are available, as well as two-way pagers that have the ability to send and receive email, numeric pages, and SMS messages. Filter bank for digital hearing: A filter bank is an array of band-pass filters that process has analysis and synthesis part.

Challenges Interfacing between synchronous and asynchronous a) Many devices available now are synchronous in nature. b) Special circuits are needed to align them.  Lack of expertise.  Lack of tools. Engineers are not trained in these fields.  Academically, no courses available

Conclusions Clock less chip in asynchronous circuit has much great advantage over clocked chips. The obvious reasons for their super performance and average speed, low power consumption, less heat and noise generated are in great demand of the current market of electronic and computing world. This is a very new area of research , design and testing but if more scientists and engineers are dedicated to this, then for surety it the future technology for mobile electronic devices.

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